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http://dx.doi.org/10.6109/jkiice.2012.16.9.1847

1V 1.6-GS/s 6-bit Flash ADC with Clock Calibration Circuit  

Kim, Sang-Hun (금오공과대학교 대학원 전자공학과)
Hong, Sang-Geun (LIG 넥스원)
Lee, Han-Yeol (금오공과대학교 대학원 전자공학과)
Park, Won-Ki (전자부품연구원)
Lee, Wang-Yong (LIG 넥스원)
Lee, Sung-Chul (전자부품연구원)
Jang, Young-Chan (금오공과대학교 대학원 전자공학과)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.16, no.9, 2012 , pp. 1847-1855 More about this Journal
Abstract
A 1V 1.6-GS/s 6-bit flash analog-to-digital converter (ADC) with a clock calibration circuit is proposed. A single track/hold circuit with a bootstrapped analog switch is used as an input stage with a supply voltage of 1V for the high speed operation. Two preamplifier-arrays and each comparator composed of two-stage are implemented for the reduction of analog noises and high speed operation. The clock calibration circuit in the proposed flash ADC improves the dynamic performance of the entire flash ADC by optimizing the duty cycle and phase of the clock. It adjusts the reset and evaluation time of the clock for the comparator by controlling the duty cycle of the clock. The proposed 1.6-GS/s 6-bit flash ADC is fabricated in a 1V 90nm 1-poly 9-metal CMOS process. The measured SNDR is 32.8 dB for a 800 MHz analog input signal. The measured DNL and INL are +0.38/-0.37 LSB, +0.64/-0.64 LSB, respectively. The power consumption and chip area are $800{\times}500{\mu}m2$ and 193.02mW.
Keywords
Flash ADC; clock calibration; duty cycle; single track/hold; resistor averaging network; comparator;
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