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Design of a Spread Spectrum Clock Generator for DisplayPort  

Lee, Hyun-Chul (School of Electronic and Electrical Engineering, Inha University)
Kim, Tae-Ho (School of Electronic and Electrical Engineering, Inha University)
Lee, Seung-Won (School of Electronic and Electrical Engineering, Inha University)
Kang, Jin-Ku (School of Electronic and Electrical Engineering, Inha University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.46, no.7, 2009 , pp. 68-73 More about this Journal
Abstract
This paper describes design and implementation of a spread spectrum clock generator (SSCG) for the DisplayPort. The proposed architecture generates the spread spectrum clock using a sigma-delta fractional-N PLL. The SSCG uses a digital End order MASH 1-1 sigma-delta modulator and a 9bit Up/Dn counter. By using MASH 1-1 sigma-delta modulator, complexity of circuit and chip area can be reduced. The advantage of sigma-delta modulator is the better control over modulation frequency and spread ratio. The SSCG generates dual clock rates which are 270MHz and 162MHz with 0.25% down-spreading and triangular waveform frequency modulation of 33kHz. The peak power reduction is 11.1dBm at 270MHz. The circuit has been designed and fabricated using in 0.18$\mu$m CMOS technology. The chip occupies 0.620mm$\times$0.780mm. The measurement results show that the fabricated chip satisfies the DispalyPort standard.
Keywords
Spread Spectrum clock; SSCG; PLL; modulation ratio; DisplayPort;
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