• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.18-27
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• 2010

In this paper, a 1.2V 7-bit 1GSPS A/D converter with offset self-calibration is proposed. The proposed A/D converter structure is based on the folding-interpolation whose folding rate is 2, interpolation rate is 8. Further, for the purpose of improving the chip performance, an offset self-calibration circuit is used. The offset self-calibration circuit reduce the variation of the offset-voltage，due to process mismatch, parasitic resistor, and parasitic capacitance. The chip has been fabricated with a 1.2V 65nm 1-poly 6-metal CMOS technology. The effective chip area is $0.87mm^2$ and the power dissipates about 110mW at 1.2V power supply. The measured SNDR is about 39.1dB when the input frequency is 250MHz at 800MHz sampling frequency. The measured SNDR is 3dB higher than the same circuit without any calibration.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.7
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• pp.620-626
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• 2015

In this paper, a 2~6 GHz wideband GaN power amplifier MMIC is designed and fabricated using a second-order all-pass filter for input impedance matching and an LC parallel resonant circuit for minimizing an output reactance component of the transistor. The second-order all-pass filter used for wideband lossy matching is modified in an asymmetric configuration to compensate the effect of channel resistance of the GaN transistor. The power amplifier MMIC chip that is fabricated using a $0.25{\mu}m$ GaN HEMT foundry process of Win Semiconductors, Corp. is $2.6mm{\times}1.3mm$ and shows a flat linear gain of about 13 dB and input return loss of larger than 10 dB. Under a saturated power mode, it also shows output power of 38.6~39.8 dBm and a power-added efficiency of 31.3~43.4 % in 2 to 6 GHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.2 s.117
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• pp.213-218
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• 2007

In this paper, we propose the design and fabrication on high frequency CMOS VCO for DS-UWB(Direct-Sequence Ultra-WideBand) applications using 0.18 ${\mu}m$ process. The complementary cross-coupled LC oscillator architecture which is composed of PMOS, NMOS symmetrically, is designed for improving the phase noise characteristic. The resistor is used instead of current source that reduce the 1/f noise of current source. The high-speed buffer is needed for measuring the output characteristic of VCO using spectrum analyzer, therefore the high-speed inverter buffer is designed with VCO. A fabricated core VCO size is $340{\mu}m{\times}535{\mu}m$. The VCO is tunable between 7.09 and 7.52 GHz and has a phase noise lower than -107 dBc/Hz at 1-MHz offset over entire tuning range. The measured harmonic suppression is 32 dB. The VCO core circuit draws 2.0 mA from a 1.8 V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.45-51
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• 2011

This paper presents a wideband low-noise amplifier (LNA) covering 800MHz~5.8GHz for various wireless communication standards by utilizing in a 0.13um CMOS technology. Particularly, the LNA consists of two stages to improve the low-noise characteristics, that is, a cascode input stage and an output buffer with noise cancellation technique. Also, a feedback resistor is exploited to help achieve wideband impedance matching and wide bandwidth. Measure results demonstrate the bandwidth of 811MHz~5.8GHz, the maximum gain of 11.7dB within the bandwidth, the noise figure of 2.58~5.11dB. The chip occupies the area of $0.7{\times}0.9mm^2$, including pads. DC measurements reveal the power consumption of 12mW from a single 1.2V supply.

• Journal of IKEEE
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• v.24 no.1
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• pp.319-325
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• 2020

In this paper, a discontinuous-conduction mode (DCM) DC-DC buck converter is presented for mobile device applications. The buck converter consists of compensator for stable operations, pulse-width modulation (PWM) logic, and power switches. In order to achieve small hardware form-factor, the number of off-chip components should be kept to be minimum, which can be realized with simple and efficient frequency compensation and digital soft start-up circuits. Burst-mode operation is included for preventing the efficiency from degrading under very light load condition. The DCM DC-DC buck converter is fabricated with 0.18-um BCDMOS process. Programmable output with external resistors is typically set to be 1.8V for the input voltage between 2.8 and 5.0V. With a switching frequency of 1MHz, measured maximum efficiency is 92.6% for a load current of 100mA.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.7
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• pp.1442-1447
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• 2004

In this paper, a 6-Bit CMOS Folding and Interpolating AD Converter is presented. The converter is considered to be useful as an integrated part of a VLSI circuit handling both analog and digital signals as in the case of HDD or LAN applications. A built-in analog circuit for VLSI of a high-speed data communication requires a small chip area, low power consumption, and fast data processing. The proposed folding and interpolating AD Converter uses a very small number of comparators and interpolation resistors, which is achieved by cascading a couple of folders working in different principles. This reduced number of parts is a big advantage for a built-in AD converter design. The design is based on 0.25m double-poly 2 metal n-well CMOS process. In the simulation, with the applied 2.5V and a sampling frequency of 500MHz, the measurements are as follows: power consumption of 27mw, INL and DNL of $\pm$0.1LSB, $\pm$0.15LSB each, SNDR of 42dB with an input signal of 10MHz.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.7 no.1
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• pp.20-25
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• 2014

There are several severe problems for LED device, the next generation's economy green lighting: as the temperature increases, the lamp efficiency decreases; if the temperature is over $80^{\circ}C$, the lifetime of lighting decreases; Red Shift phenomenon that wavelength of spectrum line moves toward long wavelength occurs; and optical power decreases as $T_j$ increases. Thus, Heat sink design that can minimize the heat of LED device is currently in progress. While the thermal resistance of COB Type LED was reduced by direct coupling of LED chip to the board, residential 13.5W requires Heat sink in order resolve heat issue. This study designed Heat Sink suitable for residential 13.5W COB LED down-light and selected the optimum Fin thickness through flow simulation that packaged the designed Heat Sink and 13.5W COB. And finally it analyzed and evaluated the thermal modes using contacting thermometer.

• Transactions of the Korean Society of Mechanical Engineers
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• v.13 no.4
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• pp.604-610
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• 1989

This paper is concerned with the machinability of fine ceramics(Al$_{2}$O$_{3}$) by using sintered diamond tools. For this purpose, ceramics cutting experiments under various cutting conditions such as cutting speed, feed rate, and others were carried out. The main results are follows : (1) During the cutting of fine ceramics, the used tools were found to be slightly chattering at cutting speed of 70m/min, and at cutting speed of higher than this I found the fine ceramics difficult to be cut. (2) When I used a tool with large nose radius, there occured a small amount of wear on the flank of the tool. However, at the early stage of fine ceramics cutting, the tools with smaller nose radii were required mainly to prevent the chipping of the ceramics. (3) When the materials were dry-cut, the appropriate cutting speel was found to be lower than 40m/min, and when the materials were dry-cut, I could cut them without any difficulty even at the speed of 70m/min, the surface roughness of ceramics cut at the speed of 70m/min was considerly fine. (4) It is generally believed that the principal cutting force is the largest in the case of steels cutting, but I found the thrust cutting force to be larger than any other cutting forces in the case of ceramics cutting.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.4
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• pp.826-832
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• 2004

A CMOS 8 bit folding and interpolating ADC for an embedded system inside VLSI is presented in this paper. This folding ADC uses the 2 stage architecture for improving of nonlinearity. repeating the folding and interpolating twice. At a proposed structure, a transistor differential pair operates on the second folder. A ADC with 2 stage architecture reduces the number of comparators and resisters. So it is possible to provide small chip size, low power consumption and high operating speed. The design technology is based on fully standard 0.25m double-Poly 2 metal n-well CMOS Process. The simulated Power consumption is 45mW with an applied voltage of 2.5V and sampling frequency of 250MHz. The INL and DNL are within <ㅆㄸㅌ>$\pm$0.2LSB, respectively. The SNDR is approximately 45dB for input frequency of 10MHz.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.34 no.2
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• pp.126-129
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• 2021

We fabricated plate typed shunt resistors composed of carbon nanotube (CNT) and metal alloy for measuring DC current. CNT plates were prepared from dispersed CNT/Urethane solution by squeezing method. Cu/Ni alloys were prepared from composition-designed alloy wires for adjusting the temperature coefficient of resistance (TCR) by pressing them. As well, we fabricated a hybrid resistor by squeezing the CNT/Urethane solution on the metal alloy plate directly. In order to confirm the composition ratio of the Cu/Ni alloy, we used an energy-dispersed X-ray spectroscopy (EDX). Cross-section and surface morphology were analyzed by using a scanning electron microscopy (SEM). Finally, we measured the initial resistance of 2.35 Ω at 25℃ for the CNT paper resistor, 7.56 mΩ for the alloy resistor, and 7.38 mΩ for the hybrid resistor. The TCR was also measured to be -778.72 ppm/℃ at the temperature range between 25℃ to 125℃ for the CNT paper resistor, 824.06 ppm/℃ for the alloy resistor, and 17.61 ppm/℃ for the hybrid resistor. Some of the hybrid resistors showed a near-zero TCR of 1.38, -2.77, 2.66, and 5.49 ppm/℃, which might be the world best-value ever reported. Consequently, we could expect an error-free measurement of the DC current using this resistor.