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A 250MS/s 8 Bit CMOS folding and Interpolating AD Converter with 2 Stage Architecture  

이돈섭 (두원공과대학 소프트웨어개발과)
곽계달 (두원공과대학 소프트웨어개발과)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.8, no.4, 2004 , pp. 826-832 More about this Journal
Abstract
A CMOS 8 bit folding and interpolating ADC for an embedded system inside VLSI is presented in this paper. This folding ADC uses the 2 stage architecture for improving of nonlinearity. repeating the folding and interpolating twice. At a proposed structure, a transistor differential pair operates on the second folder. A ADC with 2 stage architecture reduces the number of comparators and resisters. So it is possible to provide small chip size, low power consumption and high operating speed. The design technology is based on fully standard 0.25m double-Poly 2 metal n-well CMOS Process. The simulated Power consumption is 45mW with an applied voltage of 2.5V and sampling frequency of 250MHz. The INL and DNL are within <ㅆㄸㅌ>$\pm$0.2LSB, respectively. The SNDR is approximately 45dB for input frequency of 10MHz.
Keywords
ADC; AD converter;
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  • Reference
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