• Journal of Advanced Marine Engineering and Technology
• /
• v.33 no.8
• /
• pp.1254-1260
• /
• 2009

CDMA tele-Controller system is designed with a low power consumption 8 bit microcontroller, ATmega 2560. ATmega 2560 microcontroller consists of 4 UART (Universal asynchronous receiver/transmitter) ports, 4 kbytes EEPROM, 256 kbytes flash memory, 4 kbytes SRAM. 4 URAT is used for CDMA modem, communication for GPS module, EEPROM is used for saving a configuration for program running, a flash memory of 256 kbytes is used for storing a F/W(Firm Ware), and SRAM is used for stack, storing memory of global variables while program running. We have tested the communication distance between the coast station and sea by the fabricated control board using 800 MHz CDMA modem and GPS module, which is building for the navigational aid management system by remote control. As a results, the receiving signal strength is above -80 dBm, and then the characteristics of the control board implemented more than 10 km in the distance of the communication.

• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.777-780
• /
• 2005

모바일 오디오 적용을 위한 저전력 ${\Sigma}{\Delta}$ Modulator 에 대한 설계와 layout 을 보였다. 전체 구조는 3 차 단일 피드백 루프이며, 해상도는 16bit 을 갖는다. 샘플링 주파수에 따른 Over-sampling Ratio 는 128(46kHz) 또는 64(96kHz) 가 되도록 하였다. 차동 구조를 사용한 3 차 ${\Sigma}{\Delta}$ modulator 내의 적분기에 사용된 Op-Amp 는 DC-Gain 을 높이기 위해서 Gain-boosting 기법이 적용되었다. ${\Sigma}{\Delta}$ modulator 의 기준 전압은 전류 모드 Band-Gap Reference 회로에서 공급이 되며, PVT(Process, Voltage, Temperature) 변화에 따른 기준 전압의 편차를 보정하기 위하여, binary 3bit 으로 선택하도록 하였다. DAC 에서 사용되는 단위 커패시터의 mismatch 에 의한 성능 감소를 막기 위해, DAC 신호의 경로를 임의적으로 바꿔주는 scrambler 회로를 이용하였다. 4bit Quantizer 내부의 비교기 회로는 고해상도를 갖도록 설계하였고, 16bit thermometer code 에서 4bit binary code 변환시 발생하는 에러를 줄이기 위해 thermometer-to-gray, gray-to-binary 인코딩 방법을 적용하였다. 0.18um CMOS standard logic 공정 내 thick oxide transistor(3.3V supply) 공정을 이용하였다. 입력 전압 범위는 2.2Vp-p,diff. 이며, Typical process, 3.3V supply, 50' C 시뮬레이션 조건에서 2Vpp,diff. 20kHz sine wave 를 입력으로 할 때 SNR 110dB, THD 는 -95dB 이상의 성능을 보였고, 전류 소모는 6.67mA 이다. 또한 전체 layout 크기는 가로 1100um, 세로 840um 이다.

• Journal of the Korean Society of Propulsion Engineers
• /
• v.3 no.4
• /
• pp.12-22
• /
• 1999

Operation of an electromagnetic shaker system using a Class-D amplifier may cause unacceptable electromagnetic interference to another electronic system, requiring the user to take whatever steps are necessary to correct the interference. A differential amplifier in a Class-D amplifier is used to decrease the effect of a common-mode noise voltage in a shaker system. To prevent a ground loop, a transformer is inserted in another shaker system. These methods show reduction of the unwanted vibration which has occurred before. A transformer in a charge amplifier was used to prevent a ground loop in a shaker system using a Class-AB amplifier a few years ago, but it was susceptible of noise in a shaker system using a Class-D amplifier. Hence we corrected a ground loop between a charge amplifier and a vibration control/analysis system without a transformer. The usefulness of this approach is illustrated by the results of experiments.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.12
• /
• pp.71-79
• /
• 2013

This paper describes a 12.5 Gb/s low-power receiver design with equalizer adaptation. The receiver adapts to channel and chip process variation by adaptation circuit using sampler and serializer. The adaptation principle is explained. It describes technique receiving ground referenced differential signal of voltage-mode transmitter for low-power. The CTLE(Continuous Time Linear Equalizer) having 17.6 dB peaking gain to remove long tail ISI caused channel with -21 dB attenuation. The voltage margin is 210 mV and the timing margin is 0.75 UI in eye diagram. The receiver consumes 0.87 mW/Gb/s low power in 45 nm CMOS technology.

• Journal of the Korean Society for Nondestructive Testing
• /
• v.19 no.6
• /
• pp.426-432
• /
• 1999

A plus-point eddy current test(ECT) probe was developed to examine the defects on the welds of pumps, valves, and pipings which are the major components of the electric power plants, non-destructive evaluation (NDE) techniques for detecting and sizing the flaws were studied adapting this probe. Differential plus-point ECT probe is consists of two "I"-type coils crossed each other and has an advantage having a small influence on the sensitivity by lift-off variation to the conventional types of probe. The specimens with crack-like electro discharge machining(EDM) notches on the weld of type 304 stainless-steel were fabricated in order to evaluate the plus-point ECT probe response to the flaws. NDE techniques to detect and size the flaws and estimate the flaw type were established with this specimens.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.7
• /
• pp.493-502
• /
• 2001

This paper propose a new built-in current sensor(BICS) for current testing that has some advantages compared with conventional logic testing. The designed BICS detects the fault in circuit under test (CUT) and makes a Pass/Fail signal by comparison between CUT current and duplicated inverter current. The proposed circuit consists of a differential amplifier, a comparator and a inverter. It requires 10 MOSFETs and 3 inverters. Since the designed BICS do not require the extra clock, the added extra pin is only one output pin. The mode selection is not used in this circuit. Therefore we can apply the circuit to on-line testing. The validity and effectiveness are verified through the HSPICE simulation of circuits with defects. When CUT is a 8$\times$8 parallel multiplier, area overhead of the BICS is about 4.34%.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.18 no.3
• /
• pp.643-650
• /
• 2014

A hardware implementation of phase calculator for extracting 3D depth image from TOF(Time-Of-Flight) sensor is described. The designed phase calculator adopts redundant binary number systems and a pipelined architecture to improve throughput and speed. It performs arctangent operation using vectoring mode of DCORDIC(Differential COordinate Rotation DIgital Computer) algorithm. Fixed-point MATLAB simulations are carried out to determine the optimal bit-widths and number of iteration. The phase calculator has ben verified by FPGA-in-the-loop verification using MATLAB/Simulink. A test chip has been fabricated using a TSMC $0.18-{\mu}m$ CMOS process, and test results show that the chip functions correctly. It has 82,000 gates and the estimated throughput is 400 MS/s at 400Mhz@1.8V.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.5 s.335
• /
• pp.31-38
• /
• 2005

The architecture and the implementation details of a UTMI(USB2.0 Transceiver Macrocell Interface) compatible USB2.0 transceiver chip were presented. To confirm the validation of the incoming data in noisy channel environment, a squelch state detector and a current mode Schmitt-trigger circuit were proposed. A current mode output driver to transmit 480Mbps data on the USB cable was designed and an on-die termination(ODT) which is controlled by a replica bias circuit was presented. In the USB system using plesiochronous clocking, to compensate for the frequency difference between a transmitter and a receiver, a synchronizer using clock data recovery circuit and FIFO was designed. The USB cable was modeled as the lossy transmission line model(W model) for circuit simulation by using a network analyzer measurements. The USB2.0 PHY chip was implemented by using 0.25um CMOS process and test results were presented. The core area excluding the IO pads was $0.91{\times}1.82mm^2$. The power consumptions at the supply voltage of 2.5V were 245mW and 150mW for high-speed and full-speed operations, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2011.10a
• /
• pp.423-424
• /
• 2011

This paper has proposed a 920 MHz RF front-end for IEEE 802.15.4g SUN (Smart Utility Network) systems. The proposed 920 MHz RF front-end consists of a driver amplifier, a low noise amplifier, and a RF switch. In the TX mode, the driver amplifier has been designed as a single-ended topology to remove a transformer which causes a loss of the output power from the driver amplifier. In addition, a RF switch is located in the RX path not the TX path. In the RX mode, the proposed low noise amplifier can provide a differential output signal when a single-ended input signal has been applied to. A LC resonant circuit is used as both a load of the drive amplifier and a input matching circuit of the low noise amplifier, reducing the chip area. The proposed 920 MHz RF Front-end has been implemented in a 0.18-um CMOS technology. It consumes 3.6 mA in driver amplifier and 3.1 mA in low noise amplifier from a 1.8 V supply voltage.

• Journal of IKEEE
• /
• v.22 no.4
• /
• pp.1006-1011
• /
• 2018

This paper proposes a three level buck converter utilizing multi-bit flying capacitor voltage control. The conventional three-level buck converter can not control the flying capacitor voltage, so that the operation is unstable or the circuit for controlling the flying capacitor voltage can not be applied to the PWM mode. Also when the load current is increased, an error occurs in the inductor voltage. The proposed structure can control the flying capacitor voltage in PWM mode by using differential difference amplifier and common mode feedback circuit. In addition, this paper proposes a 3bit flying capacitor voltage control circuit to optimize the operation of the three level buck converter depending on the load current, and a triangular wave generation circuit using the schmitt trigger circuit. The proposed 3-level buck converter is designed in $0.18{\mu}m$ CMOS process and has an input voltage range of 2.7V~3.6V and an output voltage range of 0.7V~2.4V. The operating frequency is 2MHz, the load current range is 30mA to 500mA, and the output voltage ripple is measured up to 32.5mV. The measurement results show a maximum power conversion efficiency of 85% at a load current of 130 mA.