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http://dx.doi.org/10.5573/ieek.2013.50.12.071

A 12.5-Gb/s Low Power Receiver with Equalizer Adaptation  

Kang, Jung-Myung (College of Information and Communication Engineering, Sungkyunkwan University)
Jung, Woo-Chul (College of Information and Communication Engineering, Sungkyunkwan University)
Kwon, Kee-Won (College of Information and Communication Engineering, Sungkyunkwan University)
Chun, Jung-Hoon (College of Information and Communication Engineering, Sungkyunkwan University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.50, no.12, 2013 , pp. 71-79 More about this Journal
Abstract
This paper describes a 12.5 Gb/s low-power receiver design with equalizer adaptation. The receiver adapts to channel and chip process variation by adaptation circuit using sampler and serializer. The adaptation principle is explained. It describes technique receiving ground referenced differential signal of voltage-mode transmitter for low-power. The CTLE(Continuous Time Linear Equalizer) having 17.6 dB peaking gain to remove long tail ISI caused channel with -21 dB attenuation. The voltage margin is 210 mV and the timing margin is 0.75 UI in eye diagram. The receiver consumes 0.87 mW/Gb/s low power in 45 nm CMOS technology.
Keywords
수신기;이퀄라이저;적응기;저전력;슬라이서;
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Times Cited By KSCI : 1  (Citation Analysis)
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1 D. A. Johns and D. Essig, "Integrated circuits for data transmission over twisted-pair channels," IEEE Journal of Solid-State Circuits, vol. 32, pp.398-406, Mar. 1997.   DOI   ScienceOn
2 Poulton, J. et al., "A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS," IEEE Journal of Solid-State Circuits, vol. 42, no. 12, pp. 2745-2757, Dec. 2007.   DOI   ScienceOn
3 Dong Hun Shin, "A 1-mW 12-Gb/s Continuous-Time Adaptive Passive Equalizer in 90-nm CMOS," IEEE Custom Integrated Circuit Conference, pp. 117-120, Sept. 2009.
4 Jri Lee, "A 20-Gb/s Adaptive Equalizer in 0.13-um CMOS Technology," IEEE Journal of Solid-State Circuits, vol. 41, pp. 2058-2066, Sept. 2006.   DOI   ScienceOn
5 S. Gondi, et al., "A 10Gb/s CMOS adaptive equalizer for backplane applications," IEEE International Solid-State Circuits Conference, pp. 328-601, Feb. 2005.
6 Jong-Sang Choi, et al., "A 0.18-um CMOS 3.5-Gb/s Continuous-Time Adaptive Cable Equalizer Using Enhanced Low-Frequency Gain Control Method," IEEE Journal of Solid-State Circuits, vol. 39, pp. 419-425, Mar. 2004.   DOI   ScienceOn
7 Dongmyung Lee, et al., "An 8.5-Gb/s Fully Integrated CMOS Optoelectronic Receiver Using Slope-Detection Adaptive Equalizer," IEEE Journal of Solid-State Circuits, vol. 45, pp. 2861-2873, Dec. 2010.   DOI   ScienceOn
8 Yan-Bin Luo, et al., "A 250Mb/s-to-3.4Gb/s HDMI Receiver with Adaptive Loop Updating Frequencies and an Adaptive Equalizer," IEEE International Solid-State Circuits Conference, pp. 190-191, Feb. 2009.
9 Mira Lee, et al., "Low Power 4-Gb/s Receiver for GND-referenced Differential Signaling," Journal of IEEK, vol. 49, no. 9, pp. 244-250, Sept. 2012.
10 H. Uchiki, et al., "A 6Gb/s RX Equalizer Adapted Using Direct Measurement of the Equalizer Output Amplitude," IEEE International Solid-State Circuits Conference, pp. 104-599, Feb. 2008.
11 Youngsam Moon, "A 6Gbps CMOS Feed-Forward Equalizer Using A Differentially-Connected Varactor," Journal of IEEK, SD, vol. 46, no.2, pp. 64-70, Feb. 2009.   과학기술학회마을
12 C.-F. Lia, S.-I Liu, "A 40Gb/s CMOS Serial-Link Receiver with Adaptive Equalization and CDR," IEEE International Solid-State Circuits Conference, 2008.
13 H. Wang et al., "A 21-Gb/s 87-mW transceiver with FFE/DFE/linear equalizer in 65-nm CMOS technology," in IEEE Symp. VLSI Circuits Dig. Tech. Papers, pp. 50-51, June 2009.