• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.136-141
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• 2016

A phase-locked loop(PLL) with effectively increased capacitance by current modulator has been proposed. In this paper, the effective capacitance of loop filter is increased by using current modulator and it results in 1/10 reduction of capacitance in loop filter. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process. The simulation results show that the proposed PLL has the same phase noise characteristic and locking time of conventional PLL.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.154-156
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• 2016

In this paper, the proposed small size PLL works stable with the discrete loop filter which is controlled by voltage controlled oscillator's output signal. Sampling and a small size capacitor functioned negative feedback with switch does make it possible to integrate the PLL into a single chip. The proposed PLL is designed by 1.8V 0.18um CMOS process.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.698-701
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• 2016

A phase-locked loop(PLL) with effectively increased capacitance by current modulator has been proposed. In this paper, the effective capacitance of loop filter is increased by using current modulator and it results in 1/10 reduction of capacitance in loop filter. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process. The simulation results show that the proposed PLL has the same phase noise characteristic and locking time of conventional PLL.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.10
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• pp.1935-1940
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• 2016

This paper proposes a phase-locked loop (PLL) to minimize the loop filter output voltage fluctuation by using a comparator including RC time constant circuits. The voltage variation of loop filter is inputted to RC time constant circuits which have two RC time constants, large and small. While a small RC time constant circuit quickly conveys the output voltage variation of loop filter, a large RC time constant circuit conveys slowly the output voltage variation of loop filter and its output looks like constant voltage. The output signal of the comparator controls the sub charge pump and reduces the input voltage variation of voltage-controlled oscillator (VCO). Therefore, the proposed PLL generates a phase noise reduced signal. It has been designed with a 1.8V supply voltage, 0.18um multi - metal and multi - poly layer CMOS process and proved by Hspice simulation.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2022.06a
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• pp.71-73
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• 2022

다양한 미디어 서비스의 발전으로 비디오의 방대한 데이터를 효과적으로 압축할 수 있는 비디오 부호화 표준은 지속적인 발전을 하고 있다. 압축된 데이터를 다시 영상으로 복원하는 비디오 부복호화 과정에서 영상 데이터의 손실이 일어나고 그에 따른 다양한 형태의 열화가 나타나 영상의 화질을 저하한다. 이러한 열화들을 제거하여 원본 이미지에 가깝게 만들기 위해서 인루프 필터 과정을 비디오 부호화 표준에서 포함하고 있다. 이에 최근 영상처리 및 컴퓨터 비전 분야에서는 널리 사용되는 인공 신경망을 적용하여 효과적인 필터링을 하는 방법을 제시한다. 본 논문에서는 비디오 부호화 시 인루프 필터링에서 자기 참조를 통한 화질 개선 방법에 대해 연구하였다. 이를 위하여 트랜스포머 기반의 화질 개선 네트워크를 제안하고 기존 부호화 방법과 비교하였다. 인루프 필터링을 통해 화질을 향상하여 주관적 화질을 개선할 뿐만 아니라 객관적 부호화 효율을 증가시키는 방법을 개발하였다.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.7
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• pp.82-88
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• 2014

An available capacitance increasing phase-locked loop(PLL) with two voltage controlled oscillator gains has been proposed. In this paper, the available capacitance of loop filter is increased by using two positive/negative gains of voltage controlled oscillator (VCO). It results in 1/10 reduction in the size of loop filter capacitor. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process. The simulation results show that the proposed PLL has the same phase noise characteristic and a locking time of conventional PLL.

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.1922-1923
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• 2002

본 논문은 편광 유지 광섬유 루프 미러를 이용한 색분산 보상 필터의 제안과 이의 응용에 관한 것이다. 제안된 필터는 구성이 간단하고, 편광 의존성이 낮으며 하나의 장비로 여러 채널의 신호를 동시에 분산 보상할 수 있는 장점이 있다. 실험에 사용된 커플러의 파워-커플링 계수를 조절하면 그룹 딜레이 기울기를 조절할 수 있다. 그리고 n개의 편광 유지 광섬유 루프 미러클 연결하면 필터의 손실이 커지지만 커플링 계수의 조절을 통해 필터 특성을 변화시킬 수 있다. 이와 같은 특성을 이용하면 제안된 필터를 동적 분산 보상기로 이용할 수 있다. 논문에서는 파워-커플링 계수의 변화에 따른 필터의 그룹 딜레이 기울기의 변화를 계산한 그래프와 실험 결과 데이터를 비교 제시하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2380-2386
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• 2013

A PLL with an unipolar charge pump and a loop filter consisting of sample-hold capacitor and 2nd-order RC filter has been proposed. The goal of the proposed PLL is the suppression of reference spur which is caused by charge pump mismatch. It also improves phase noise characteristic. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.335-342
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• 2016

This paper proposes efficient hardware structure of in-loop filter for a high-performance HEVC (High Efficiency Video Coding) encoder. HEVC uses in-loop filter consisting of deblocking filter and SAO (Sample Adaptive Offset) to improve the picture quality in a reconstructed image due to a quantization error. However, in-loop filter causes an increase in complexity due to the additional encoder and decoder operations. A proposed in-loop filter is implemented as a three-stage pipeline to perform the deblocking filtering and SAO operation with a reduced number of cycles. The proposed deblocking filter is also implemented as a six-stage pipeline to improve efficiency and performs a new filtering order for efficient memory architecture. The proposed SAO processes six pixels parallelly at a time to reduce execution cycles. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 131K logic gates in TSMC $0.13{\mu}m$ process. At 164MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 60fps in real time.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.2
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• pp.339-344
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• 2017

A novel structure of phase locked loop (PLL) which has small size and fast locking time with Early-late detector, Duty-rate modulator, and Lock status indicator (LSI) is proposed in this paper. The area of loop filter usually occupying the larger portion of the chip is minimized using a single small capacitor. While the conventional PLL with a single capacitor loop filter cannot work stably, the proposed PLL with two charge pumps works stably because the output voltage waveform of the proposed a single capacitor loop filter is the same as the output voltage waveform of the conventional 2nd-order loop filter. The two charge pumps are controlled by the Early-late detector which detects early-late status of UP and DN signals, and Duty-rate modulator which generates a steady duty-rate signal. Fast locking time is achieved using LSI. It has been simulated and proved by HSPICE in a CMOS $0.18{\mu}m$ 1.8V process.