1 |
P. K. Hanumolu, M. Brownlee, K. Mayaram and U. K. Moon, "Analysis of Charge-Pump Phase-Locked Loops," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, no. 9, pp. 1665-1674, Sep. 2004.
DOI
|
2 |
J. Craninckx and M. Steyaert, "A fully integrated CMOS DCS-1800 frequency synthesizer," IEEE International Solid-State Circuits Conference. Digest of Technical Papers, vol. 33, no. 12, pp. 2054-2065, Dec. 1998.
|
3 |
Y. Koo, H. Huh, Y. Cho, J. Lee, J. Park, D. Jeong, and W. Kim, "A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems," IEEE Journal of Solid-State Circuits, vol. 37, no. 5, pp. 536-542, May 2002.
DOI
|
4 |
B. Catli, A. Nazemi, T. Ali, S. Fallahi, Y. Liu, J. Kim, M. Abdul-Latif, M. R. Ahmadi, H. Maarefi, A. Momtaz, and N. Kocaman, "A 2sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications," Custom Integrated Circuits Conference, pp. 1-4, 2013.
|
5 |
M. Ghasemzadeh, S. Mahdavi, A. Zokaei, K. Hadidi, "A New Adaptive PLL to Reduce the Lock Time in 0.18 technology," MIXDES - 23rd International Conference Mixed Design of Integrated Circuits and Systems, pp. 140-142, June 2016.
|
6 |
J. Dunning et al., "An all-digital phase-locked loop with 50-cycle lock time suitable for high-performance microprocessors," IEEE Journal of Solid-State Circuits, vol. 30, no. 4, pp. 412-422, Apr. 1995.
DOI
|
7 |
Y. S. Choi, S. J. An, "Loop filter voltage variation compensated PLL with charge pump," Journal of Korea Institute of Information and Communication Engineering, vol. 20, no. 10, pp. 1935-1940, Oct. 2016.
DOI
|
8 |
Y. S. Choi, H. H. Choi, T. H. Kwon, "An Adaptive Bandwidth Phase Locked Loop with Locking Status Indicator," Proceedings. The 9th Russian-Korean International Symposium on Science and Technology, pp. 826-829, July 2005.
|