Browse > Article
http://dx.doi.org/10.6109/jkiice.2017.21.2.339

Fast locking single capacitor loop filter PLL with Early-late detector  

Ko, Ki-Yeong (Department of Electronic Engineering, Pukyong National University)
Choi, Yong-Shig (Department of Electronic Engineering, Pukyong National University)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.21, no.2, 2017 , pp. 339-344 More about this Journal
Abstract
A novel structure of phase locked loop (PLL) which has small size and fast locking time with Early-late detector, Duty-rate modulator, and Lock status indicator (LSI) is proposed in this paper. The area of loop filter usually occupying the larger portion of the chip is minimized using a single small capacitor. While the conventional PLL with a single capacitor loop filter cannot work stably, the proposed PLL with two charge pumps works stably because the output voltage waveform of the proposed a single capacitor loop filter is the same as the output voltage waveform of the conventional 2nd-order loop filter. The two charge pumps are controlled by the Early-late detector which detects early-late status of UP and DN signals, and Duty-rate modulator which generates a steady duty-rate signal. Fast locking time is achieved using LSI. It has been simulated and proved by HSPICE in a CMOS $0.18{\mu}m$ 1.8V process.
Keywords
PLL; fast locking time; small size chip; single capacitor;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
1 P. K. Hanumolu, M. Brownlee, K. Mayaram and U. K. Moon, "Analysis of Charge-Pump Phase-Locked Loops," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, no. 9, pp. 1665-1674, Sep. 2004.   DOI
2 J. Craninckx and M. Steyaert, "A fully integrated CMOS DCS-1800 frequency synthesizer," IEEE International Solid-State Circuits Conference. Digest of Technical Papers, vol. 33, no. 12, pp. 2054-2065, Dec. 1998.
3 Y. Koo, H. Huh, Y. Cho, J. Lee, J. Park, D. Jeong, and W. Kim, "A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems," IEEE Journal of Solid-State Circuits, vol. 37, no. 5, pp. 536-542, May 2002.   DOI
4 B. Catli, A. Nazemi, T. Ali, S. Fallahi, Y. Liu, J. Kim, M. Abdul-Latif, M. R. Ahmadi, H. Maarefi, A. Momtaz, and N. Kocaman, "A 2sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications," Custom Integrated Circuits Conference, pp. 1-4, 2013.
5 M. Ghasemzadeh, S. Mahdavi, A. Zokaei, K. Hadidi, "A New Adaptive PLL to Reduce the Lock Time in 0.18${\mu}m$ technology," MIXDES - 23rd International Conference Mixed Design of Integrated Circuits and Systems, pp. 140-142, June 2016.
6 J. Dunning et al., "An all-digital phase-locked loop with 50-cycle lock time suitable for high-performance microprocessors," IEEE Journal of Solid-State Circuits, vol. 30, no. 4, pp. 412-422, Apr. 1995.   DOI
7 Y. S. Choi, S. J. An, "Loop filter voltage variation compensated PLL with charge pump," Journal of Korea Institute of Information and Communication Engineering, vol. 20, no. 10, pp. 1935-1940, Oct. 2016.   DOI
8 Y. S. Choi, H. H. Choi, T. H. Kwon, "An Adaptive Bandwidth Phase Locked Loop with Locking Status Indicator," Proceedings. The 9th Russian-Korean International Symposium on Science and Technology, pp. 826-829, July 2005.