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http://dx.doi.org/10.6109/jkiice.2016.20.10.1935

Loop Filter Voltage Variation Compensated PLL with Charge Pump  

An, Seong-Jin (Department of Electronic Engineering, Pukyong National University)
Choi, Yong-shig (Department of Electronic Engineering, Pukyong National University)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.20, no.10, 2016 , pp. 1935-1940 More about this Journal
Abstract
This paper proposes a phase-locked loop (PLL) to minimize the loop filter output voltage fluctuation by using a comparator including RC time constant circuits. The voltage variation of loop filter is inputted to RC time constant circuits which have two RC time constants, large and small. While a small RC time constant circuit quickly conveys the output voltage variation of loop filter, a large RC time constant circuit conveys slowly the output voltage variation of loop filter and its output looks like constant voltage. The output signal of the comparator controls the sub charge pump and reduces the input voltage variation of voltage-controlled oscillator (VCO). Therefore, the proposed PLL generates a phase noise reduced signal. It has been designed with a 1.8V supply voltage, 0.18um multi - metal and multi - poly layer CMOS process and proved by Hspice simulation.
Keywords
Phase locked loop; Sub charge pump; Voltage variation compensation; Comparison time constant;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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