Journal of the Institute of Electronics and Information Engineers (전자공학회논문지)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Increased Effective Capacitance with Current Modulator in PLL

Current Modulator를 이용하여 유효커패시턴스를 크게 하는 위상고정루프

  • 김혜진 (부경대학교 전자공학과) ;
  • 최영식 (부경대학교 전자공학과)
  • Received : 2015.09.07
  • Accepted : 2016.04.01
  • Published : 2016.04.25
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Abstract

A phase-locked loop(PLL) with effectively increased capacitance by current modulator has been proposed. In this paper, the effective capacitance of loop filter is increased by using current modulator and it results in 1/10 reduction of capacitance in loop filter. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process. The simulation results show that the proposed PLL has the same phase noise characteristic and locking time of conventional PLL.

본 논문에서는 Current Modulator를 이용하여 루프 필터 커패시턴스 유효 용량을 배가 시켜 칩 크기를 줄일 수 있는 위상 고정루프를 제안하였다. 제안된 위상고정루프에서는 Current Modulator로 루프 필터의 커패시턴스 유효 용량을 배가 시켜 루프 필터 커패시터 크기를 1/10로 줄였다. 제안된 위상고정루프는 1.8V $0.18{\mu}m$ CMOS 공정을 이용하여 설계되었다. 시뮬레이션 결과는 기존 구조와 같은 잡음 특성과 위상고정 시간을 보여주었다.

Keywords

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