• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.05a
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• pp.790-791
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• 2014

본 논문에서는 처음 레이아웃을 접하는 학생들이 쉽게 레이아웃을 할 수 있도록 논리게이트의 입력 수에 따른 소스/드레인 접합면의 개수 및 출력 단자에 연결되는 드레인 접합면의 개수를 간단한 수식으로 설명하고자 한다. 일반적으로 디지털 회로에서는 직렬로 연결되는 트랜지스터의 경우 하나의 접합면으로 트랜지스터의 소스와 또 다른 트랜지스터의 드레인으로 동작하도록 레이아웃 된다. 그리고 출력 단자에 연결되는 드레인 접합면의 개수를 줄어야만 논리게이트의 동작속도를 향상시킬 수 있다. 그러므로 출력단자를 구성하는 드레인 접합의 개수를 수식으로 제시하고 설명함으로서 초보자도 쉽게 레이아웃을 할 수 있도록 하고자 한다.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.1
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• pp.29-34
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• 2010

This paper proposes a new parity-preserving reversible logic gate. It is a parity-preserving reversible logic gate, that is, the party of the outputs matches that of the inputs. In recent year, reversible logic gate has emerged as one of the important approaches for power optimization with its application in low CMOS design, quantum computing and nono-technology. We show that our proposed parity-preserving reversible logic gate is much better in terms of number of reversible logic gates, number of garbage-outputs and hardware complexity with compared ti the exiting counterpart.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.54-58
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• 2007

Development of high performance LTPS TFTs contributed to open up new SOP technology with various digital circuits integrated in display panels. This work introduces the current mode logic(CML) gate design method with which one can replace slow CMOS logic gates. The CML inverter exhibited small logic swing, fast response with high power consumption. But the power consumption became compatible with CMOS gates at higher clock speed. Due to small current values in CML, layout area is smaller than the CMOS counterpart even though CML uses larger number of devices. CML exhibited higher noise immunity thanks to its non-inverting and inverting outputs. Multi-input NAND/AND and NOR/OR gates were implemented by the same circuit architecture with different input confirugation. Same holds for MUX and XNOR/XOR CML gates. We concluded that the CML gates can be designed with few simple circuits and they can improve power consumption, chip area, and speed of operation.

• Proceedings of the Korea Information Processing Society Conference
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• 2018.10a
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• pp.5-7
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• 2018

VLSI(Very large scale integration) 기술을 통한 트랜지스터의 소형화를 통해 CMOS 집적 회로의 성능은 지속적으로 발전해 왔다. 이와 같은 기술 발전에 따라 집적 회로를 구성하는 디지털 논리 요소 또한 진화를 하고 있다. 디코더는 부호화된 정보를 다시 부호화되기 전으로 되돌아가는 처리를 하는 디지털 논리 요소이며 컴퓨터 설계에서 많이 사용되는 핵심 요소이다. 본 논문에서는 양자점 셀룰라 오토마타(Quantum Cellular-Automata, QCA)를 사용하여 인에이블 입력을 가진 2-to-4 디코더를 제안하였다. 4-입력 유니버설 게이트의 하나의 입력을 1로 고정시켜 3-입력 NOR 게이트로 사용하며, 입력 값 X와 입력 값 Y의 중복된 배선 수를 감소시키고 한 배선으로 두 게이트에 입력을 연결하여 디코더의 배선 수와 배선 교차부를 최소화한다. 제안안하는 4-to-2 인에이블 디코더는 기존 디코더보다 셀의 개수와 클럭수를 감소시켜 디코더의 성능을 더 효율적으로 향상시켰다. 이를 통해 고속 회로 설계에 활용 및 높은 성능을 기대 할 수 있으며 QCA 연구에 기여할 수 있을 것으로 전망 한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.3 s.333
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• pp.43-50
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• 2005

In this paper, quaternary logic gates using Down literal circuit(DLC) has been designed, and then synchronous Quaternary un/down counter using those gates has been proposed The proposed counter consists of T-type quaternary flip flop and 1-of-2 threshold-t MUX, and T-type quaternary flip flop consists of D-type quaternary flip flop and quaternary logic gates(modulo-4 addition gates, Quaternary inverter, identity cell, 1-of-4 MUX). The simulation result of this counter show delay time of 10[ns] and power consumption of 8.48[mW]. Also, assigning the designed counter to MVL(Multiple-valued Logic) circuit, it has advantages of the reduced interconnection and chip area as well as easy expansion of digit.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.675-676
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• 2013

This paper presents a design method for multiple-output combinational digital logic systems using time domain based on multiplexing and common multi-terminal extension decision diagrams. The common multi-terminal extension decision diagrams represents extension valued multiple-output functions, while time domain based on multiplexing systems transmit several signals on a single lines. The proposed method can reduce the 1)hardware, 2)logic levels and 3)pins. In the logic system design, we use two types of decision diagrams, that is the common binary decision diagrams and common multi-terminal extension decision diagrams.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1288-1293
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• 2005

This paper presents a design method for multiple-output combinational digital logic systems using time domain based on multiplexing(TDBM) and common multi-terminal extension decision diagrams(CMTEDD). The CMIEDDs represents extension valued multiple-output functions, while TDBM systems transmit several signals on a single lines. The proposed method can reduce the 1)hardware, 2)logic levels and 3)pins. In the logic system design, we use two types of decision diagrams(DDs), that is the common binary decision diagrams(CBDDs) and CMTEDDs. Also, we propose an algorithms to derive common multiple-terminal binary decision diagrams(CMTBDD) from CBDDs, and CMTEDDs from CMTBDDs. The CMTEDDs over CBDDs is more compactness in terms of number of non-terminal nodes, where the nodes for output selection variables are not included in the non-terminal nodes. In the logic design, each non-terminal nodes of an CBDDs and an CMTEDDs is realized by a multiplexer(MUX). In addition, we compare the proposed TDBM realization with the conventional one.

• Proceedings of the Korean Society of Computer Information Conference
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• 2014.01a
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• pp.271-272
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• 2014

현재 디지털 시스템 설계가 필요한 모든 유한 상태머신을 설계에는 필수적 밀리 모델이나 무어 모델이 들어간다. 그러나 각각의 기기와 기능에 따라서 밀리 모델과 무어 모델 중 어느 모델이 디지털 논리회로 설계에 효율적인지 판단이 모호한 상황이다. 이를 위해 본 논문에서는 유한 상태머신의 하나인 벤딩머신을 대상으로 밀리 모델과 무어 모델을 사용하여 설계한 후, 설계의 복잡도와 구현 게이트 수를 구하여 각 모델의 효율성에 대해 비교 분석하고자 한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.107-116
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• 2009

Quantum-dot Cellular Automata (QCA) is one of the most promising next generation nanoelectronic devices which will inherit the throne of CMOS which is the domineering implementation technology for large scale low power digital systems. In late 1990s, the basic operations of the QCA cell were already demonstrated on a hardware implementation. Also, design tools and simulators were developed. Nevertheless, its design technology is not quite ready for ultra large scale designs. This paper proposes a new approach which enables the QCA designs to inherit the verification methodologies and tools of CMOS designs, as well. First, a set of disciplinary rules strictly restrict the cell arrangement not to deviate from the predefined structures but to guarantee the deterministic digital behaviors is proposed. After the gate and interconnect structures of. the QCA design are identified, the signal integrity requirements including the input path balancing of majority gates, and the prevention of the noise amplification are checked. And then the digital logic is extracted and stored in the OpenAccess common engineering database which provides a connection to a large pool of CMOS design verification tools. Towards validating the proposed approach, we designed a 2-bit adder, a bit-serial adder, and an ALU bit-slice. For each design, the digital logic is extracted, translated into the Verilog net list, and then simulated using a commercial software.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.57-65
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• 2014

This paper presents a framework that is based on a reconfigurable macro-model of current-mode logic (CML) high-speed digital circuits enabling equation-based design optimization. The proposed macro-model is compatible with geometric programming, thereby enabling constraint-driven top-level power optimization. The proposed optimization framework is applied to a design of CML based serial-link transmitter with user-defined design specifications as an example of high speed digital circuits using 45nm and 90nm CMOS technology. The proposed optimization framework can derive a design with optimal power efficiency for given transistor technology nodes.