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New Parity-Preserving Reversible Logic Gate  

Kim, Sung-Kyoung (Graduate School of Information Management and Security, Korea University)
Kim, Tae-Hyun (The Attached Institute of ETRI)
Han, Dong-Guk (Department of Mathematics, Kookmin University)
Hong, Seok-Hie (Graduate School of Information Management and Security, Korea University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SC / v.47, no.1, 2010 , pp. 29-34 More about this Journal
Abstract
This paper proposes a new parity-preserving reversible logic gate. It is a parity-preserving reversible logic gate, that is, the party of the outputs matches that of the inputs. In recent year, reversible logic gate has emerged as one of the important approaches for power optimization with its application in low CMOS design, quantum computing and nono-technology. We show that our proposed parity-preserving reversible logic gate is much better in terms of number of reversible logic gates, number of garbage-outputs and hardware complexity with compared ti the exiting counterpart.
Keywords
Reversible logic gate; parity-preserving; fault tolerant; quantum computing; nano-technology;
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