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Design of Synchronous Quaternary Counter using Quaternary Logic Gate Based on Neuron-MOS  

Choi Young-Hee (Dept. of Electricis Engineering, InHa University)
Yoon Byoung-Hee (Dept. of Electricis Engineering, InHa University)
Kim Heung-Soo (Dept. of Electricis Engineering, InHa University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.42, no.3, 2005 , pp. 43-50 More about this Journal
Abstract
In this paper, quaternary logic gates using Down literal circuit(DLC) has been designed, and then synchronous Quaternary un/down counter using those gates has been proposed The proposed counter consists of T-type quaternary flip flop and 1-of-2 threshold-t MUX, and T-type quaternary flip flop consists of D-type quaternary flip flop and quaternary logic gates(modulo-4 addition gates, Quaternary inverter, identity cell, 1-of-4 MUX). The simulation result of this counter show delay time of 10[ns] and power consumption of 8.48[mW]. Also, assigning the designed counter to MVL(Multiple-valued Logic) circuit, it has advantages of the reduced interconnection and chip area as well as easy expansion of digit.
Keywords
MVL; Quaternary; DLC;
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