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http://dx.doi.org/10.5573/ieie.2014.51.11.057

Design Optimization of CML-Based High-Speed Digital Circuits  

Jang, Ikchan (College of Information and Communication Engineering, Sungkyunkwan University)
Kim, Jintae (Department of Electronics Engineering, Konkuk University)
Kim, SoYoung (College of Information and Communication Engineering, Sungkyunkwan University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.51, no.11, 2014 , pp. 57-65 More about this Journal
Abstract
This paper presents a framework that is based on a reconfigurable macro-model of current-mode logic (CML) high-speed digital circuits enabling equation-based design optimization. The proposed macro-model is compatible with geometric programming, thereby enabling constraint-driven top-level power optimization. The proposed optimization framework is applied to a design of CML based serial-link transmitter with user-defined design specifications as an example of high speed digital circuits using 45nm and 90nm CMOS technology. The proposed optimization framework can derive a design with optimal power efficiency for given transistor technology nodes.
Keywords
Geometric Programming;
Citations & Related Records
Times Cited By KSCI : 3  (Citation Analysis)
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