The purpose of this work is to investigate the interface characteristics of hydrogenated amorphous silicon thin films prepared by PECVD and photo-induced CVD and to examine the annealing effects of ultraviolet irradiation on hydrogenated amorphous silicon thin films which were degraded by visible light illumination. The interface layer thickness of films deposited by photo-induced CVD was about 600-900.angs. while that by PECVD was about 1000-1300.angs.. These results can show that the quality of interface layer in photo induced CVD film is better than that in PECVD sample. The electrical properties are improved by ultraviolet irradiation on visible light soaked a-Si:H films using photo-CVD light sources, probably due to the fact that UV generates phonons in a-Si:H films and anneal the meta stable defects.

A bilayer film consisting of a layer of a-Se$_{75}$ Ge$_{25}$ with a surface layer of silver -100[.angs.] thick and a monolayer film of a-Se$_{75}$ Ge$_{25}$ are irradiated with 9[keV] Ga$^{+}$ ion beam. The Ga$^{+}$ ion (10$^{16}$ [ions/cm$^{2}$] exposed a-Se$_{75}$ Ge$_{25}$ and Ag/a-Se$_{75}$ Ge$_{25}$ thin films show an increase in optical absorption, and the absorption edge on irradiation with shifts toward longer wavelength. The shift toward longer wavelength called a "darkening effect" is observed also in film exposure to optical radiation(4.5*10$^{20}$ [photons/cm$^{2}$]). The 0.3[eV] edge shift for ion irradiation films is about twice to that obtained on irradiation with photons. These large changes are primarily due to structural changes, which lead to high etch selectivity and high sensitivity.

In the manufacturing of VLSI circuits, variations of device characteristics due to the slight differences in process parameters drastically aggravate the performances of fabricated devices. Therefore, it is very important to establish optimal process conditions in order to minimize deviations of device characteristics. In this paper, we used one-dimensional process simulator, SUPREM-II, and two dimensional device simulator, MINIMOS 4.0 in order to extract optimal process parameter which can minimize changes of the device characteristics caused by process parameter variation in the case of short channel nMOSFET and pMOSFET device. From this simulation, we have derived the dependence relations between process parameters and device characteristics. Here, we have suggested a method to extract process parameters from design trend curve(DTC) obtained by these dependence relations. And we have discussed short channel effects and device limitations by scaling down MOSFET dimensions.

The role of ZnS buffer layer not only suppresses chemical reactions between emission material and insulating material but also alters the luminescence and the crystallinity of the emission layer, if ZnS buffer layer was sandwiched between emission layer and insulating layer of electroluminescent device. In this research, we fabricated ZnS thin film with rf magnetron sputter system by varying rf power 100, 200W, substrate temperature 100, 150, 200, 250.deg. C and post-annealing temperature 200, 300, 400, 500.deg. C and analysed X-ray diffraction pattern, transmission spectra and cross section by SEM photograph for seeking the optimal crystallization condition of ZnS buffer layer. As a result, increasing the rf power, the crystallinity of ZnS thin film was improved. It was found that the ZnS thin film had better properties than anything else when fabricated with the following conditions ; rf power 200W, substrate temperature 150.deg. C, and post-annealing temperature 400.deg. C. ZnS thin film had the transmittance more than 80% in visible range. So it is suitable to use as a buffer layer of electroluminescent devices.

SONOS EEPROM chips, containing several SONOSFET nonvolatile memories of various channel size, have been fabricated on the basis of the existing n-well CMOS processing technology for 1 Mbit DRAM ($1.2\mu\textrm{m}$.m design rule). All the SONOSFET memories have the triple insulated-gate consisting of 30.angs. tunneling oxide, 205.angs. nitride and 65.angs. blocking oxide. The miniaturization of the devices for the higher density EEPROM and their characteristics alterations accompanied with the scaling-down have been investigated. The stabler operating characteristics were attained by increasing the ratio of the channel width to length. Also, the transfer, switching, retention and degradation characteristics of the most favorable performance devices were presented and discussed.

Indium, element of group III, was refined by using zone refining for high purity refinement. We have found the impurities of T1, Zn, Fe, Cd, Pb, Ni, Cu, Sn in the refined indium with ICP-AES, so that 3.9 weight ppm of T1 was reduced to less than 1 ppm, 1.0 weight ppm of Zn was reduced to 0.7 ppm, 2.8 weight ppm of Cd was reduced to 2.5 ppm and 14.0 weight ppm of Sn was reduced to 6.7 ppm with 5 melten zone passes only. 3.9 weight ppm of T1 was reduced to less than 1 ppm, 1.0 weight ppm of Zn was reduced to 0.3 ppm, 2.8 weight ppm of Cd was reduced to less than 1.0 ppm and 14.0 weight ppm of Sn was reduced to 0.4 ppm after vacuum baking with 5 melten zone passes. The surface morpholgy of metal Indium thin film in each conditions showed that porosities were reduced in the front of sampled ingot after vacuum baking with 5 zone melten zone passes. The average electrical resistivity of Indium thin film was reduced from 1.4*10$^{-3}$ .ohm.-cm in Indium origin ingot to 7.9*10$^{-6}$ .ohm.-cm after zone refined with 5 melten zone passes.

Electrical conduction phenomena of $C_{22}$-quinolium(TCNQ) Langmuir- Blodgett(LB) films are reported through a study of current-voltage(I-V) characteristics along a perpendicular direction. The I-V characteristics were investigated by applying a step or a pulse voltage to the specimen as well as changing temperatures in the range of 20-250[.deg. C] It show an ohmic behavior in low-electric field, and a nonohmic behavior in high-electric field. This nonohmic behavior has been interpreted in terms of a conduction mechanism of space-charge limited current and Schottky effect. When the electric field is near the strength of 10$_{6}$ V/cm, there occur anomalous phenomena similar to breakdown. When step or pulse voltage is applied, the breakdown voltage shifts to the higher one as the step or pulse time width becomes shorter. To see the influence of temperature, current was measured as a function of temperature under the several bias voltages, which are lower than that of breakdown. It shows that the current increases to about 103 times near 60-70[.deg. C], and remains constant for a while up to around 150[.deg. C] and then suddenly drops. We have also performed a DSC(differential scanning calorimetry) measurement with $C_{22}$-quinolium(TCNQ) powder in the range of 30-300[.deg. C]. These results imply that the anomalous phenomena occuring in the high electric field are caused by the electrical and internal thermal effect such as a joule heating.ating.

The multi-dielectric layer SiOz/Si3N4/SiO2(ONO) is used to scale down the memory device. In this paper, the change of composition in ONO layer due to the process condition and the conduction mechanism are observed. The composition of the oxide film grown through the oxidation of nitride film is analyzed using auger electron spectroscopy(AES). AES results show that oxygen concentration increases at the interface between oxide and nitride layers as the thickness -of the top oxide layer increases. Results of I-V measurement show that the insulating properties improve as the thickness of the top oxide layer increases. But when the thickness of the nitride layer decreases below 63.angs, insulating peoperties of film 28.angs. of top oxide and film 35.angs. turn over showing that insulating property of film 28.angs. of top oxide is better than that of film 35.angs. of top oxide. This phenomenon of turn over is thought as the result of generation of surface state due to oxygen flow into nitride during oxidation process. As the thickness of the top oxide and nitride increases, the electrical breakdown field increases, but when the thickness of top oxide reaches 35.angs, the same phenomenon of turn over occurs. Optimum film thickness for scaled multi-layer dielectric of memory device SONOS is estimated to be 63.angs. of nitride layer and 28.angs. of top oxide layer. In this case, maximum electrical breakdown field and leakage current are 18.5[MV/cm] and $8{\times}{10^-12}$[A], respectively.

The rapid thermal annealing effects of Sol-Gel derived ferroelectric PZT thin films were investigated. It was found that rapid thermal annealing(RTA) of spin coated thin films on silicon typically >$800^{\circ}C$ for about 1 min. was changed to the perovskite phase. Rapid thermally annealed films recorded maximum remanent polarization of about 5 .mu.C/cm$^{2}$, coercive field of around 30kV/cm. The switching time for polarization reversal was about 220ns. The films of RTA process showed smooth surface, and high breakdown voltages of over 1 MV/cm and resistivity of $1{\times}{10^12}$ .ohm.cm at 1 MV/cm. It was verified that the polarization reversal of the PZT film was varied partially with applying the multiple short pulse.

DRAM(Dynamic Random Access Memory)은 반도체 소자중 가장 대표적인 기억소자로, switch역활을 하는 1개의 transistor와 data의 전하를 축적하는 1개의 capacitor로 구성된 단순한 구조와 고집적화에 용이하다는 이점을 바탕으로, supercomputer에서 가전제품 및 산업기기에 이르기 까지 널리 이용되어왔다. 한편으로 DRAM사업은 고가의 장치사업으로 조기시장 진입을 위하여 초기에 막대한 자본투자, 급속한 기술발전, 짧은 life cycle, 가격급락등이 심하여, 시한내 투자회수가 이루어져야 하는 위험도가 큰 기회사업이라는 양면성도 가지고 있다. 이러한 관점때문에 새로운 DRAM기술은 매 세대마다 끊임없이 빠른 속도로 개발되어왔다. 그러나 sub-micron이하의 DRAM세대로 갈수록 그에 대한 신기술은 점차 어렵게 되어가고, 한편으로는 system의 다양화에 따른 요구도 강하여, 이제는 통상적인 DRAM의 고집적화/저가의 전략만으로는 생존하기 어려운 실정이므로 개발전략도 수정하여야만 할 것이다. 이러한 어려운 기술한계를 극복하기 위하여 새로운 소자기술 및 공정개발에 대한 breakthrough가 이루어져야 할 것이다. 이러한 관점에서 현재까지의 DRAM개발 추이와 향후의 기술방향에 관하여 몇가지 중요한 item을 설정하여 논의해 보기로 한다.

1967년 Wegener등과 Khang등이 각각 구조 및 동작원리가 다른 비휘발성 반도체 메모리(nonvolatile semiconductor memory)를 최초로 개발, 도입한 이후 3세대째를 보내고 있는 현재, 메모리는 반도체산업의 선봉으로써 여전히 공정기술(processing technology)을 이끌며, 시장점유율, 응용범위등에서 주도적 위치를 차지하고 있다. 한편, 최근의 컴퓨터 시스템은 소형화, 저전력화, 고속화, 내충격성 등 기술적 측면에서 뿐만 아니라 소프트웨어적으로도 급격히 발전하고 있다. 이에 따라 메모리부분에 있어서도 기존의 자기 하드디스크 메모리(magnetic hard disk memory)의 한계를 극복하기 위해서 반도체 메모리로서 대체가 더욱 요구되고 있다. 이와같은 상황에서 EEPROM(electrically erasable and programmable ROM)은 상주 시스템내에서도 전기적 방법에 의해 사용자가 임으로 기록/소거(write/erase)할 수 있을 뿐만 아니라 전원이 제거된 상테에서도 기억상태를 유지할 수 있는 비휘발성이라는 점에서 차세대 반도체 메모리 부문의 주역으로서 주목받고 있다. 따라서, 본 고에서는 20세기를 보내며 반도체메모리의 새로운 장을 열어가는 EEPROM의 기술현황 및 전망에 관해 살펴보고자 한다.