• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.450-452
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• 2016

The effect of channel doping on L-shaped Tunneling Field-Effect Transistors (TFETs) have been investigated by 2D TCAD simulation. When the source doping is over $10^{20}cm^{-3}$, the subthreshold swing (SS) is abruptly decreased, and when drain doping concentration is below $10^{18}cm^{-3}$, the leakage current in the negative voltage is reduced.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.172-178
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• 2016

In this paper, we propose a sub-10 nm Ge/GaAs heterojunction-based tunneling field-effect transistor (TFET) with vertical band-to-band tunneling (BBT) operation for ultra-low-power (LP) applications. We design a stack structure that is based on the Ge/GaAs heterojunction to realize the vertical BBT operation. The use of vertical BBT operations in devices results in excellent subthreshold characteristics with a reduction in the drain-induced barrier thinning (DIBT) phenomenon. The proposed device with a channel length ($L_{ch}$) of 5 nm exhibits outstanding LP performance with a subthreshold swing (S) of 29.1 mV/dec and an off-state current ($I_{off}$) of $1.12{\times}10^{-11}A/{\mu}m$. In addition, the use of the highk spacer dielectric $HfO_2$ improves the on-state current ($I_{on}$) with an intrinsic delay time (${\tau}$) because of a higher fringing field. We demonstrate a sub-10 nm LP switching device that realizes a good S and lower $I_{off}$ at a lower supply voltage ($V_{DD}$) of 0.2 V.

• Journal of Electrical Engineering and Technology
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• v.12 no.6
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• pp.2324-2332
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• 2017

This paper presents the electrical performances of novel AlGaSb/InGaAs heterojunction-based vertical-tunneling field-effect transistor (VTFET). The device performance was investigated in views of the on-state current ($I_{on}$), drain-induced barrier thinning (DIBT), and subthreshold swing (SS) as the gate length ($L_G$) was scaled down. The proposed TFET with a $L_G$ of 5 nm operated with an $I_{on}$ of $1.3mA/{\mu}m$, a DIBT of 40 mV/V, and an SS of 23 mV/dec at a drain voltage ($V_{DS}$) of 0.23 V. The proposed TFET provided approximately 25 times lower DIBT and 12 times smaller SS compared with the conventional $L_G$ of 5 nm TFET. The AlGaSb/InGaAs VTFET showed extremely high scalability and strong immunity against short-channel effects.

• Journal of Electrical Engineering and Technology
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• v.9 no.2
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• pp.655-661
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• 2014

In this paper, a new two dimensional (2D) analytical modeling and simulation for a surrounding gate tunnel field effect transistor (TFET) is proposed. The Parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions and analytical expressions for surface potential and electric field are derived. This electric field distribution is further used to calculate the tunneling generation rate and thus we numerically extract the tunneling current. The results show a significant improvement in on-current characteristics while short channel effects are greatly reduced. Effectiveness of the proposed model has been confirmed by comparing the analytical results with the TCAD simulation results.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.243-244
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• 2017

This paper introduces about the difference between the tunneling currents in the 1D and 2D directions for the calculation of the band-to-band tunneling currents of the tunneling field effect transistors. In the two-dimensional tunneling, diagonal tunneling is not calculated in the one-dimensional tunneling so that more accurate tunneling current can be calculated. Simulation results show that the tunneling in the two - dimensional direction has no effect on the voltage above the threshold voltage, but it affects the subthreshold swing below the threshold voltage.

• Proceeding of EDISON Challenge
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• 2015.03a
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• pp.350-353
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• 2015

최근 에너지 효율과 소형화측면에서 한계를 보이는 Metal-Oxide-Semiconductor Field-Effect Transistor(MOSFET)을 대체할 수 있는 소자로 Tunneling FET(TFET)이 주목받고 있다. 본 논문에서는 탄소나노튜브(Carbon Nanotube, CNT) TFET을 시뮬레이션하여 전자회로의 기본 단위인 인버터(Inverter)를 설계한다. 설계한 인버터의 성능을 CNT-MOSFET 인버터와 비교하여 저전력 디지털 회로로써의 가능성을 확인한다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.475-476
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• 2019

L-shaped tunneling field-effect-transistor (LTFET) is considered a superior device over conventional TFETs. However, experimentally demonstrated LTFET demonstrated poor subthreshold characteristics which was attributed to trap-assisted-tunneling (TAT) caused by presence of trap states. In this paper, TAT mechanism in the experimentally demonstrated LTFET is investigated with the help of band diagram and TAT recombination rate (GTAT).

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.4
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• pp.272-277
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• 2011

The ambipolar behavior of tunneling field-effect transistors (TFETs) has been investigated quantitatively by introducing a novel parameter: ambipolarity factor (${\nu}$). It has been found that the malfunction of TFET can result from the ambipolar state which is not on- or off- state. Therefore, the effect of ambipolar behavior on the device performance should be parameterized quantitatively, and this has been successfully evaluated as a function of device structure, gate oxide thickness, supply voltage, drain doping concentration and body doping concentration by using ${\nu}$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.3
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• pp.224-236
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• 2013

This work presents a comparative study of four Double Gate tunnel FET (DG-TFET) architectures: conventional p-i-n DG-TFET, p-n-p-n DG-TFET, a gate dielectric engineered Heterogate (HG) p-i-n DG-TFET and a new device architecture with the merits of both Hetero Gate and p-n-p-n, i.e. HG p-n-p-n DG-TFET. It has been shown that, the problem of high gate capacitance along with low ON current for a p-i-n TFET, which severely hampers the circuit performance of TFET can be overcome by using a p-n-p-n TFET with a dielectric engineered Hetero-gate architecture (i.e. HG p-n-p-n). P-n-p-n architecture improves the ON current and the heterogeneous dielectric helps in reducing the gate capacitance and suppressing the ambipolar behavior. Moreover, the HG architecture does not degrade the output characteristics, unlike the gate drain underlap architecture, and effectively reduces the gate capacitance.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.6
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• pp.551-555
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• 2013

Linearity characteristics of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs) have been compared with those of high-k-only and $SiO_2$-only TFETs in terms of IIP3 and P1dB. It has been observed that the optimized HG TFETs have higher IIP3 and P1dB than high-k-only and $SiO_2$-only TFETs. It is because HG TFETs show higher transconductance ($g_m$) and current drivability than $SiO_2$-only TFETs and $g_m$ less sensitive to gate voltage than high-k-only TFETs.