• Journal of IKEEE
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• v.19 no.2
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• pp.232-236
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• 2015

Super-junction trench MOSFET (SJ TMOSFET) devices are well known for lower specific on-resistance and high breakdown voltage (BV). For a conventional power MOSFET (metal-oxide semiconductor field-effect transistor) such as trench double-diffused MOSFET (TDMOSFET), there is a tradeoff relationship between specific on-state resistance and breakdown voltage. In order to overcome the tradeoff relationship, a SJ TMOSFET structure is suggested, but sensing the temperature distribution of TMOSFET is very important in the application since heat is generated in the junction area affecting TMOSFET. In this paper, analyzing the temperature characteristics for different number bonding for SJ TMOSFET with an embedded temperature sensor is carried out after designing the diode temperature sensor at the surface of SJ TMOSFET for the class of 100 V and 100 A for a BLDC motor.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.109-114
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• 2013

Power MOSFET (metal-oxide semiconductor field-effect transistor) are widely used in power electronics applications, such as BLDC (Brushless Direct Current) motor and power module, etc. For the conventional power MOSFET device structure, there exists a tradeoff relationship between specific on-state resistance and breakdown voltage. In order to overcome the tradeoff relationship, a non-uniform super-junction (SJ) trench MOSFET (TMOSFET) structure for an optimal design is proposed in this paper. It is required that the specific on-resistance of non-uniform SJ TMOSFET is less than that of uniform SJ TMOSFET under the same breakdown voltage. The idea with a linearly graded doping profile is proposed to achieve a much better electric field distribution in the drift region. The structure modelling of a unit cell, the characteristic analyses for doping density, and potential distribution are simulated by using of the SILVACO TCAD 2D device simulator, Atlas. As a result, the non-uniform SJ TMOSFET shows the better performance than the uniform SJ TMOSFET in the specific on-resistance at the class of 100V.

• Journal of IKEEE
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• v.25 no.2
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• pp.350-355
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• 2021

IGBT is a power semiconductor device that contains both MOSFET and BJT structures, and it has fast switching speed of MOSFET, high breakdown voltage and high current of BJT characteristics. IGBT is a device that targets the requirements of an ideal power semiconductor device with high breakdown voltage, low V_CE-SAT, fast switching speed and high reliability. In this paper, we analyzed Gate oxide thickness, Trench Gate Width, and P+Emitter width, which are the top process parameters of 1,200V Trench Gate Field Stop IGBT, and suggested the optimized top process parameters. Using the Synopsys T-CAD Simulator, we designed IGBT devices with electrical characteristics that has breakdown voltage of 1,470 V, V_CE-SAT 2.17 V, Eon 0.361 mJ and Eoff 1.152 mJ.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.3
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• pp.190-193
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• 2013

Power MOSFET and Power IGBT is develop in power savings, high efficiency, small size, high reliability, fast switching, low noise. Power MOSFET can be used high-speed switching transistors devices. Power MOSFET is devices the voltage-driven approach switching devices are design to handle on large power, power supplies, converters. In this paper, design the 80V MOSFET Planar Gate type, and design the Trench Gate type for realization of low on-resistance. For both structures, by comparing and analyzing the results of the simulation and characterization.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.88-89
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• 2009

In this paper, we investigated about wet cleaning effect as deep trench formation methods for Power chip devices. Deep trench structure was classified by two methods, PSU (Poly Stick Up) and Non-PSU structure. In this paper, we could remove residue defect during wet. cleaning after deep trench etch process for non-PSU structure device as to change wet cleaning process condition. V-SEM result showed void image at the trench bottom site due to residue defect and residue component was oxide by EDS analysis. In order to find the reason of happening residue defect, we experimented about various process conditions. So, defect source was that oxide film was re-deposited at trench bottom by changed to hydrophobic property at substrate during hard mask removal process. Therefore, in order to removal residue defect, we added in-situ SCI during hard mask removal process, and defect was removed perfectly. And WLR (Wafer Level Reliability) test result was no difference between normal and optimized process condition.

• Journal of IKEEE
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• v.27 no.1
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• pp.103-108
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• 2023

This research was carried out experiments with changing processes and design parameters to optimally design a SiC-based 1200V power MOSFET, and then, essential electrical characteristics were derived. In order to secure the excellence of the trench gate type SiC power MOSFET device to be designed, electrical characteristics were derived by designing it under conditions such as planner gate SiC power MOSFET, and it was compared with the trench gate type SiC power MOSFET device. As a result of the comparative analysis, the on-resistance while maintaining the yield voltage was 1,840mΩ, for planner gate power MOSFET and to 40mΩ for trench gate power MOSFET, respectively, indicating characteristics more than 40 times better. It was judged that excellent results were derived because the temperature resistance directly affects energy efficiency. It is predicted that the devices optimized through this experiment can sufficiently replace the IGBT devices generally used in 1200V class, and that since the SiC devices are wide band gap devices, they will be widely used to apply semiconductors for vehicles using devices with excellent thermal characteristics.

• Transactions on Electrical and Electronic Materials
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• v.17 no.4
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• pp.222-226
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• 2016

This paper investigated the trench process, unified field limit ring, and other products for the development of a 500 V-level unified trench gate power MOSFET. The optimal base chemistry for the device was found to be SF₆. In SEM analysis, the step process of the trench gate and field limit ring showed outstanding process results. After finalizing device design, its electrical characteristics were compared and contrasted with those of a planar device. It was shown that, although both devices maintained a breakdown voltage of 500 V, the Vth and on-state voltage drop characteristics were better than those of the planar type.

• Journal of IKEEE
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• v.19 no.1
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• pp.110-117
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• 2015

In this paper, a novel trench power MOSFET using a Separate-W-gated technique MOSFET (SWFET) is proposed. Because the SWFET has a very low $Q_{GD}$ compared to other forms of technology, it can be applied to high-speed power systems. The results found that the SWFET-applied $Q_{GD}$ was decreased by 40% when compared to simply using the more conventional trench gate MOSFET. $C_{ISS}$ (input capacitance : $C_{GS}+C_{GD}$), $C_{OSS}$ (output capacitance : $C_{GD}+C_{DS}$) and $C_{RSS}$ (reverse recovery capacitance : $C_{GD}$) were improved by 24%, 40%, and 50%, respectively. The switching characteristics of the inverter circuit shows a 24.9% enhancement of reverse recovery time, and the power efficiency of the DC-DC buck converter increased by 14.2%. In addition, the proposed SWFET does not require additional process steps and There was no degradation in the electrical performance of the current-voltage and on-resistance.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.12
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• pp.2258-2263
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• 2006

In this parer, hump characteristics of short-channel nMOSFETs induced by moistures of the ILD(inter-layer dielectric) layer in the shallow trench isolation (STI) process are investigated and the method for hump suppression is proposed Using nMOSFETs with various types of the gate and a measurement of TDS-APIMS (Thermal Desorption System-Atmospheric Pressure ionization Mass Spectrometry), hump characteristics were systematically analyzed and the systemic analysis based hump model was presented; the ILD layer over poly-Si gate of nMOSFET generates moistures, but they can't diffuse out of the SiN layer due to the upper SiN layer. Consequently, they diffuses into the edge between the gate and STI and induces short-channel hump. In order to eliminate moisture in the ILD layer by out-gassing method, the annealing process prior to the deposition of the SiN layer was carried out. As the result, short-channel humps of the nMOSFETs were successfully suppressed.

• Journal of Electrical Engineering and Technology
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• v.9 no.3
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• pp.843-847
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• 2014

In Super Junction (SJ) MOSFETs, charge balance is the most important issue of the SJ fabrication process. In order to achieve the best electrical characteristics, such as breakdown voltage and on-resistance, the N-type and P-type drift regions must be fully depleted when the drain bias approaches the breakdown voltage, which is known as the charge balance condition. In conventional charge balance analysis, based on multi-epi process SJ MOSFETs, analytical model has only N, P pillar width and doping concentration parameter. But applying a conventional charge balance principle to trench filling process, easier than Multi-epi process, is impossible due to the missing of the trench angle parameter. To achieve much more superior characteristics of on-resistance in trench filling SJ MOFET, the appropriate trench angle is necessary. So in this paper, modulated charge balance analysis is proposed, in which a trench angle parameter is added. The proposed method is validated using the TCAD simulation tool.