• 전기의세계
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• 제22권1호
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• pp.42-51
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• 1973

The contriving equivalent circuit of single phase induction motor which does not separate the primary leakage reactance and the secondary leakage reactance by the revolving field theory, and the graphically calculating method of the characteristics with T-type circle diagram of three phase induction motor which does not suppose the primary leakage reactance can be drawn up only by the no load test, the lock test, and measuring the resistance of stator winding are suggested in this paper. The method which can calculate the parameters of the equivalent circuit and the characteristics with no load test, lock test and measuring resistance of stator windings is suggested in this paper. Considered the exciting current in lock test, we could calculate very accurate characteristics of the single phase induction motor.

• 한국정보통신학회논문지
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• 제9권5호
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• pp.1089-1095
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• 2005

본 논문에서는 5GHz 저잡음 증폭기(LNA)의 성능 측정을 위한 새로운 형태의 저가 BIST(Built-In Self-Test) 회로를 제안한다 이러한 BIST 회로는 system-on-chip (SoC) 송수신 환경에 적용될 수 있도록 설계되어 있다. 본 논문에서 제안하는 BIST 회로는 입력 임피던스, 전압이득, 잡음지수, 입력반사손실(input return loss) 및 출력 신호 대 잡음전력비(signal-to-noise ratio)와 같은 저잡음 증폭기의 주요 성능 지수를 측정 할 수 있으며, 단일 칩 위에 제작되어 있다.

• 조명전기설비학회논문지
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• 제25권6호
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• pp.75-81
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• 2011

This study aims to research and analyze the cause and countermeasures of the short-circuit test failures of the distribution transformer, which captures failure share at the highest level when carrying out its performance test. For this purpose, the research was done on the basis of 77 failure cases out of 998 tests in total performed by the Korea Electrotechnology Research Institute(KERI) from 2004 to 2010. Based on the research, the paper also includes analysis of the causes of the short-circuit test failures in its early stage of transformer development and proposes its countermeasures accordingly.

• 전력전자학회논문지
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• 제23권6호
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• pp.433-439
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• 2018

This study considers the design of a submodule test circuit for the modular multi-level converter (MMC)-based HVDC systems. A novel submodule test circuit is proposed to provide not only an AC but also a DC component to the submodule current. However, the current waveforms depend on the capacitor voltages. Therefore, determining the capacitance value of the test circuit is important. Finding a proper capacitance value is easy when the proposed analysis method is used. Simulation and experimental results show the usefulness of the proposed method.

• 전기학회논문지
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• 제56권9호
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• pp.1566-1570
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• 2007

[ $SF_6$ ] gas circuit breakers are widely used for short circuit current interruption in EHV(Extra High Voltage) or UHV(Ultra High Voltage) power systems. To develop $SF_6$ gas circuit breakers, the arc resistance value is necessary to compare experimental results to numerical ones. The arc resistance value can be obtained from a breaking test with a $SF_6$ gas circuit breaker. The direct testing or synthetic testing facility is widely used to verify the breaking ability for $SF_6$ gas circuit breakers. We employed the simplified synthetic testing facility to test a $SF_6$ gas circuit breaker prototype. The arc resistance characteristic was measured and calculated under the various experimental conditions. This arc resistance value can be used for verifying the numerical results from arc simulation in a circuit breakers.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 하계학술대회 논문집 B
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• pp.623-627
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• 1995

This paper describes analysis and optimization of Weil-Dobke synthetic testing circuit parameters, which is efficient and economical test method in high capacity AC circuit breaker. In this paper, analysis of synthetic short-circuit test circuit parameter proposed nondimensional factor that is reciprocal comparison value of circuit parameter and is not related to rated of circuit breaker, in particular, this study induce minimization of required energy of critical TRV generation specified in IEC 56 standards and present optimal design of synthetic short circuit testing facilities.

• 대한물리의학회지
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• 제7권1호
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• pp.125-135
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• 2012

Purpose : This study is designed to demonstrate the effects of circuit obstacle group gait training on walking ability and emotion in stroke patients. Methods : Twenty one patients with stroke were participated in this study. The subjects were divided into control group(n=10) and experimental group(n=11). Circuit obstacle group gait training consisted of walking around obstacles, walking over obstacles, walking up and down slopes and walking up and down stairs. Circuit obstacle group gait training was conducted five times per week, 1 hour per session, for 6 consecutive weeks. At pre-test and post-test, subjects were tested with 10 m walking test, timed up and go test, up and down 4 stairs test, depression and self esteem. Results : After 6 weeks of research, the experimental group showed statistically significant difference in all items when comparing prior to training and after training (p<.05), but the control group showed statistically significant difference in items other than depression and self esteem(p<.05). In the comparison between the two groups, the experimental group showed higher improvement than the control group in the 10 m walking test, timed up and go test, and up and down 4 stairs test, and there was statistically significant difference in decrease of degree in depression between the experimental group and control group(p<.05). Conclusion : This study have shown that circuit obstacle group gait training improves walking ability and emotion in stroke patients.

• 한국통신학회논문지
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• 제17권7호
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• pp.666-676
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• 1992

본 논문에서는 RAM에서 발생하는 모든 PSF(Pattern Sensitive Fault)를 검사하기 위한알고리즘과 테스트회로를 제안하였다. 기존의 테스트회로와 사용된 알고리즘은 RAM셀들을 연속적으로 테스트하거나 메모리의 2차원적 구조를 사용하지 못했기 때문에 많은 테스트 시간이 소요되었다. 본 논문에서는 기존의 RAM회로에 테스트를 위한 부가적인 회로를 첨가하여 병렬적으로 RAM을 테스트 하는 방법을 제안하였다. 부가적으로 첨가된 회로로는 병렬 비교기와 오류 검출기, 그룹 선택회로 이고 병렬 테스팅 위해서 수정된 디코더를 사용하였다. 또한, 효과적인 테스트 패턴을 구하기 위해 Eulerian경로의 구성방법에 대해서도 연구를 수행하였다. 결과적으로, 본 논문에서 사용한 알고리즘을 사용하면 b x w=n의 매트릭스 형태로 표현되는 RAM을 테스트하는데 325*워드라인 수 만큼의 동작이 필요하게 된다. 구현한 각 회로에 대해서 회로 시뮬레이션을 수행한 후 10 bit*32 word Testable RAM을 설계하였다.

• 전력전자학회논문지
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• 제26권3호
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• pp.214-221
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• 2021

SiC MOSFETs require a faster and more reliable short-circuit protection circuit than conventional methods due to narrow short-circuit withstand times. Therefore, this research proposes a short-circuit protection circuit using a current-sensing circuit based on Rogowski coil. The method of designing the current-sensing circuit, which is a component of the proposed circuit, is presented first. The integrator and input/output filter that compose the current-sensing circuit are designed to have a wide bandwidth for accurately measuring short-circuit currents with high di/dt. The precision of the designed sensing circuit is verified on a double pulse test (DPT). In addition, the sensing accuracy according to the bandwidth of the filters and the number of turns of the Rogowski coil is analyzed. Next, the entire short-circuit protection circuit with the current-sensing circuit is designed in consideration of the fast short-circuit shutdown time. To verify the performance of this circuit, a short-circuit test is conducted for two cases of short-circuit conditions that can occur in the half-bridge structure. Finally, the short-circuit shutdown time is measured to confirm the suitability of the proposed protection circuit for the SiC MOSFET short-circuit protection.

• 전자공학회논문지B
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• 제30B권5호
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• pp.82-89
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• 1993

In this paper, we proposed the autonomous algorithm of pseudo-exhaustive testing for the multi-level combinational logic circuits. For the processing of shared-circuit that existed in each cone-circuit when it backtracked the path from PO to PI of CUT at the conventional verification testing, the dependent relation of PI-P0 is presented by a dependence matrix so it easily partitioned the sub-circuits for the pseudo-exhaustive testing. The test pattern of sub-circuit's C-inputs is generated using a binary counter and the test pattern of I-inputs is synthesized using a singular cover and consistency operation. Thus, according to the test patterns presented with the recipe cube, the number of test pattrens are reduced and it is possible to test concurrently each other subcircuits. The proposed algorithm treated CUT's net-list to the source file and was batch processed from the sub-circuit partitioning to the test pattern generation. It is shown that the range of reduced ration of generated pseudo-exhaustive test pattern exhibits from 85.4% to 95.8% when the average PI-dependency of ISACS bench mark circuits is 69.4%.