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http://dx.doi.org/10.6113/TKPE.2018.23.6.433

Capacitance Value Analysis of Sub-module Test Circuit for MMC-based HVDC System  

Seo, Byuong-Jun (Dept. of Electrical Eng., Pukyong National University)
Park, Kwon-Sik (Dept. of Electrical Eng., Pukyong National University)
Jo, Kwang-Rae (Dept. of Electrical Eng., Pukyong National University)
Nho, Eui-Cheol (Dept. of Electrical Eng., Pukyong National University)
Kim, Heung-Geun (Dept. of Electrical Eng., Kyungpook National University)
Chun, Tae-Won (Dept. of Electrical Eng., University of Ulsan)
Kim, Tae-Jin (Power Conversion & System for Renewable Energy research Center, KERI)
Lee, Jong-Pil (Power Conversion & System for Renewable Energy research Center, KERI)
Publication Information
The Transactions of the Korean Institute of Power Electronics / v.23, no.6, 2018 , pp. 433-439 More about this Journal
Abstract
This study considers the design of a submodule test circuit for the modular multi-level converter (MMC)-based HVDC systems. A novel submodule test circuit is proposed to provide not only an AC but also a DC component to the submodule current. However, the current waveforms depend on the capacitor voltages. Therefore, determining the capacitance value of the test circuit is important. Finding a proper capacitance value is easy when the proposed analysis method is used. Simulation and experimental results show the usefulness of the proposed method.
Keywords
Modular multi-level converter; Sub-module test; HVDC;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
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