• Title/Summary/Keyword: subthreshold swing

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Anomalous Phenomena on Subthreshold Characteristics of SOI MOSFET Back Gate Voltage

  • Lee, Seung-Min;Lee, Mike-Myung-Ok
    • Proceedings of the IEEK Conference
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    • 1998.10a
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    • pp.553-556
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    • 1998
  • The 1-D numerical model and its extraction methodology are suggested and these simulation results for the S-swing as a function of back-gate voltage are well matched with the measured. S-swing characteristics are analyzed using PD-SOI devices with enough deeper regions up to substrates. The PD-SOI device doesn't have to be short channel to see the anomalous subthreshold phenomena based on the back gate bias. This results recommend to operate better SOI device performances by controlling the back gate voltages. So SOI performances will be much optimistic with proper control of the back-gate voltage for the already- proven- high- performance (APHP) SOI VLSIs.

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Trap-related Electrical Properties of GaN MOSFETs Through TCAD Simulation

  • Doh, Seung-Hyun;Hahm, Sung-Ho
    • Journal of Sensor Science and Technology
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    • v.27 no.3
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    • pp.150-155
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    • 2018
  • Three different structures of GaN MOSFETs with trap distributions, trap levels, and densities were simulated, and its results were analyzed. Two of them are Schottky barrier MOSFETs(SB-MOSFETs): one with a p-type GaN body while the other is in the accumulation mode MOSFET with an undoped GaN body and regrown source/drain. The trap levels, distributions and densities were considered based on the measured or calculated properties. For the SB-MOSFET, the interface trap distribution affected the threshold voltage significantly, but had a relatively small influence on the subthreshold swing, while the bulk trap distribution affects the subthreshold swing more.

Thickness Effects of Active Layers on the Properties of Zinc Tin Oxide Transparent Thin Film Transistors (Zinc Tin Oxide 투명 박막트랜지스터의 특성에 미치는 활성층 두께의 영향)

  • Ma, Tae Young
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.27 no.7
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    • pp.433-437
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    • 2014
  • Transparent thin film transistors were fabricated on $n^+$-Si wafers coated by $Al_2O_3/SiO_2$. Zinc tin oxide (ZTO) films deposited by rf magnetron sputtering were employed for active layers. The mobility (${\mu}s$), threshold voltage ($V_T$), and subthreshold swing (SS) dependances on ZTO thickness were analyzed. The $V_T$ decreased with increasing ZTO thickness. The ${\mu}s$ raised from $5.1cm^2/Vsec$ to $27.0cm^2/Vsec$ by increasing ZTO thickness from 7 nm to 12 nm, and then decreased with ZTO thickness above 12 nm. The SS was proportional to ZTO thickness.

Metal work function dependent photoresponse of schottky barrier metal-oxide-field effect transistors(SB MOSFETs) (금속(Al, Cr, Ni)의 일함수를 고려한 쇼트키 장벽 트랜지스터의 전기-광학적 특성)

  • Jung, Ji-Chul;Koo, Sang-Mo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2010.06a
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    • pp.355-355
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    • 2010
  • We studied the dependence of the performance of schottky barrier metal-oxide-field effect transistors(SB MOSFETs) on the work function of source/drain metals. A strong impact of the various work functions and the light wavelengths on the transistor characteristics is found and explained using experimental data. We used an insulator of a high thickness (100nm) and back gate issues in SOI substrate, subthreshold swing was measured to 300~400[mV/dec] comparing with a ideal subthreshold swing of 60[mV/dec]. Excellent characteristics of Al/Si was demonstrated higher on/off current ratios of ${\sim}10^7$ than others. In addition, extensive photoresponse analysis has been performed using halogen and deuterium light sources(200<$\lambda$<2000nm).

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Influence of Channel Length on the Performance of Poly-Si Thin-Film Transistors (다결정 실리콘 박막 트랜지스터의 성능에 대한 채널 길이의 영향)

  • 이정석;장창덕;백도현;이용재
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1999.05a
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    • pp.450-453
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    • 1999
  • In this paper, The relationship between device performance and channel length(1.5-50$\mu$m) in polysilicon thin-film transistors fabricated by SPC technology was Investigated by measuring electric Properties such as 1-V characteristics, field effect mobility, threshold voltage, subthreshold swing, and trap density in grain boundary with channel length. The drain current at ON-state increases with decreasing channel length due to increase of the drain field, while OFF-state current (leakage current) is independent of channel length. The field effect mobility decrease with channel length due to decreasing carrier life time by the avalanche injection of the carrier at high drain field. The threshold voltage and subthreshold swing decrease with channel length, and then increase in 1.5 $\mu$m increase of increase of trap density in grain boundary by impact ionization.

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Comparison of Current-Voltage Characteristics of Nanosheet FET and FinFET (Nanosheet FET와 FinFET의 전류-전압 특성 비교)

  • Ahn, Eun Seo;Yu, Yun Seop
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2022.05a
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    • pp.560-561
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    • 2022
  • In this paper, current-voltage characteristics of various types of Nanosheet FET (NSFET) and FinFET are simulated with 3D device simulator. The threshold voltage and subthreshold swing extracted from the simulated current-voltage characteristics of NSFET and FinFET were compared. Both of threshold voltage and drain current of NSFET are higher than those of FinFET. The subthreshold voltage swing (SS) of NSFET is steeper than that of FinFET.

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A New Scaling Theory for the Effective Conducting Path Effect of Dual Material Surrounding Gate Nanoscale MOSFETs

  • Balamurugan, N.B.;Sankaranarayanan, K.;Suguna, M.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.8 no.1
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    • pp.92-97
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    • 2008
  • In this Paper, we present a scaling theory for dual material surrounding gate (DMSGTs) MOSFETs, which gives a guidance for the device design and maintaining a precise subthreshold factor for given device parameters. By studying the subthreshold conducting phenomenon of DMSGTs, the effective conductive path effect (ECPE) is employed to acquire the natural length to guide the design. With ECPE, the minimum channel potential is used to monitor the subthreshold behavior. The effect of ECPE on scaling factor significantly improves the subthreshold swing compared to conventional scaling rule. This proposed model offers the basic designing guidance for dual material surrounding gate MOSFETs.

Influence of Ratio of Top and Bottom Oxide Thickness on Subthreshold Swing for Asymmetric Double Gate MOSFET (비대칭 이중게이트 MOSFET에서 상단과 하단 산화막 두께비가 문턱전압이하 스윙에 미치는 영향)

  • Jung, Hakkee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.3
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    • pp.571-576
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    • 2016
  • Asymmetric double gate(DG) MOSFET has the different top and bottom gate oxides thicknesses. It is analyzed the deviation of subthreshold swing(SS) and conduction path for the ratio of top and bottom gate oxide thickness of asymmetric DGMOSFET. SS varied along with conduction path, and conduction path varied with top and bottom gate oxide thickness. The asymmetric DGMOSFET became valuable device to reduce the short channel effects like degradation of SS. SSs were obtained from analytical potential distribution by Poisson's equation, and it was analyzed how the ratio of top and bottom oxide thickness influenced on conduction path and SS. SSs and conduction path were greatly influenced by the ratio of top and bottom gate oxide thickness. Bottom gate voltage cause significant influence on SS, and SS are changed with a range of 200 mV/dec for $0<t_{ox2}/t_{ox1}<5$ under bottom voltage of 0.7 V.

Reduction of Source/Drain Series Resistance in Fin Channel MOSFETs Using Selective Oxidation Technique (선택적 산화 방식을 이용한 핀 채널 MOSFET의 소스/드레인 저항 감소 기법)

  • Cho, Young-Kyun
    • Journal of Convergence for Information Technology
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    • v.11 no.7
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    • pp.104-110
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    • 2021
  • A novel selective oxidation process has been developed for low source/drain (S/D) series resistance of the fin channel metal oxide semiconductor field effect transistor (MOSFET). Using this technique, the selective oxidation fin-channel MOSFET (SoxFET) has the gate-all-around structure and gradually enhanced S/D extension regions. The SoxFET demonstrated over 70% reduction in S/D series resistance compared to the control device. Moreover, it was found that the SoxFET behaved better in performance, not only a higher drive current but also higher transconductances with suppressing subthreshold swing and drain induced barrier lowering (DIBL) characteristics, than the control device. The saturation current, threshold voltage, peak linear transconductance, peak saturation transconductance, subthreshold swing, and DIBL for the fabricated SoxFET are 305 ㎂/㎛, 0.33 V, 13.5 𝜇S, 76.4 𝜇S, 78 mV/dec, and 62 mV/V, respectively.

Influence on Short Channel Effects by Tunneling for Nano structure Double Gate MOSFET (나노구조 이중게이트 MOSFET에서 터널링이 단채널효과에 미치는 영향)

  • Jung, Hak-Kee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.10 no.3
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    • pp.479-485
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    • 2006
  • The double gate(DG) MOSFET is a promising candidate to further extend the CMOS scaling and provide better control of short channel effect(SCE). DGMOSFETs, having ultra thin undoped Si channel for SCEs control, ale being validated for sub-20nm scaling. A novel analytical transport model for the subthreshold mode of DGMOSFETs is proposed in this paper. The model enables analysis of short channel effect such as the subthreshold swing(SS), the threshold voltage roil-off$({\Delta}V_{th})$ and the drain induced barrier lowering(DIBL). The proposed model includes the effects of thermionic emission and quantum tunneling of carriers through the source-drain barrier. An approximative solution of the 2D Poisson equation is used for the distribution of electric potential, and Wentzel-Kramers-Brillouin approximation is used for the tunneling probability. The new model is used to investigate the subthreshold characteristics of a double gate MOSFET having the gate length in the nanometer range $(5-20{\sim}nm)$ with ultra thin gate oxide and channel thickness. The model is verified by comparing the subthreshold swing and the threshold voltage roll-off with 2D numerical simulations. The proposed model is used to design contours for gate length, channel thickness, and gate oxide thickness.