• Journal of Power Electronics
• /
• v.19 no.6
• /
• pp.1591-1600
• /
• 2019

In this paper, a practical SPICE model for an IGBT and a PiN diode is proposed based on the Finite Differential Method (FDM). Other than the conventional Fourier model and the Hefner model, the excess carrier distribution can be accurately solved by a fast FDM in the SPICE simulation tool. In order to improve the accuracy of the SPICE model, the Taguchi method is adopted to calibrate the extracted parameters. This paper presents a numerical modelling approach of an IGBT and a PIN diode, which are also verified by SPICE simulations and experiments.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.65 no.3
• /
• pp.439-444
• /
• 2016

The method for extracting the SPICE model parameter of Schottky diode under DC forward bias is proposed. A method for improving the accuracy of the SPICE model parameter at various temperatures is proposed. Three analysis steps according to the magnitude of the current is used in order to extract the parameters effectively. At each analysis step, initial parameters are calculated by using the current-voltage equations and the Levenberg-Marquardt analysis is proceeded. To verify the validity of the proposed method, the SPICE model parameters for the BAT45 and FSV1045 under DC forward bias is extracted. Schottky diode currents obtained from the proposed method shows the average relative error of 6.1% and 9% compared with the measured data for the BAT45 and FSV1045 sample at various temperatures.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.58 no.9
• /
• pp.1769-1774
• /
• 2009

An algorithm for extracting the BJT DC model parameter values for SPICE model is proposed. The nonlinear optimization method for analyzing the device I-V data using the Levenberg-Marquardt algorithm is proposed and the method for calculating initial conditions of model parameters to improve the convergence characteristics is proposed. The base current and collector current obtained from the proposed method shows the root mean square error of 6.04% compared with the measured data of the PNP BJT named 2SA1980.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.2
• /
• pp.98-103
• /
• 2003

This paper proposes new SPICE Macro-Model of Magnetic Tunnel Junction (MTJ) This Macro-Model has five I/O terminals, reproduces MTJ MR characteristics including hysteresis and behaves correctly to time varying input signals. Furthermore, this Model can be easily modified to various MTJs with different characteristics by simply varying internal parameters.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.24 no.5
• /
• pp.794-803
• /
• 1987

In this paper, the SPICE 2.G6 JFET subroutine and other related subroutines are modified for circuit simulation of GaAs MESFET IC's. The hyperbolic tangent model is used for the drain current-voltage characteristics of GaAs MESFET's and derived channel-conductance and drain-conductance model from the above current model are implemented into small-signal model of GaAs MESFET's. And, device capacitance model which consider after-pinch-off state are modified, and device charge model for SPICE 2G.6 are proposed. The result of modification is shown to be suitable for GaAs circuit simulator, showing good agreement with experimetal results. Forthermore the DC convergence of this paper is better than that of SPICE 2.G JFET subroutine. GaAs MESFET model in this paper is applied for both depletion mode GaAs MESFET and enhancement-mode GaAs MESFET without difficulty.

• The Transactions of the Korean Institute of Electrical Engineers
• /
• v.43 no.4
• /
• pp.607-612
• /
• 1994

The static and dynamic model of IGBT for the SPICE simulation has been successfully developed. The various circuit model parameters are extracted from the I-V and C-V characteristics of IGBT and implemented into our model. The static model of IGBT consists of the MOSFET, bipolar transistor and series resistance. The parameters to be extracted are the threshold voltage of MOSFET, current gain $\beta$ of bipolar transistor, and the series resistance. They can be extracted from the measured I-V characteristics curve. The C-V characteristics between the terminals are very important parameters to determine the turn-on and turn-off waveform. Especially, voltage dependent capacitance are polynomially approximated to obtain the exact turn-on and turn-off waveforms. The SPICE simulation results employing new model agree well with the experimental values.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.11 no.5
• /
• pp.347-352
• /
• 1998

In this paper, the extraction and optimization of SPICE parameters on SONOSFET for NVSM circuit design were discussed. SONOSFET devices with different channel widths and lengths were fabricated using conventional 1.2 um n-well CMOS process. And, electric properties for dc parameters and capacitance parameters were measured on wafer. SPICE parameters for the SONOSFET were extracted from the UC Berkeley level 3 model for the MOSFET. And, local optimization of Ids-Vgs curves has carried out in the bias region of subthreshold, linear, saturation respectively. Finally, the extracted SPICE parameters were optimized globally by comparing drain current (Ids), output conductance(gds), transconductance(gm) curves with theoretical curves in whole region of bias conditions. It is shown that the conventional model for the MOSFET can be applied to the SONOSFET modeling except sidewalk effect.

• Journal of information and communication convergence engineering
• /
• v.14 no.2
• /
• pp.115-121
• /
• 2016

Currently there is a lack of literature on SPICE-level models of double-gate (DG) tunnel field-effect transistors (TFETs). A DG TFET compact model is presented in this work that is used to develop a SPICE model for DG TFETs implemented with Verilog-A language. The compact modeling approach presented in this work integrates several issues in previously published compact models including ambiguity about the use of tunneling parameters A_k and B_k, and the use of a universal equation for calculating the surface potential of DG TFETs in all regimes of operation to deliver a general SPICE modeling procedure for DG TFETs. The SPICE model of DG TFET captures the drain current-gate voltage (I_ds-V_gs) characteristics of DG TFET reasonably well and offers a definite computational advantage over TCAD. The general SPICE modeling procedure presented here could be used to develop SPICE models for any combination of structural parameters of DG TFETs.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.4
• /
• pp.7-12
• /
• 2010

We have developed a SPICE compatible model of thermoelectric devices, and a parameter extracting technique only by electrical and temperature measurement by using Harman method was proposed. The proposed model and parameter extraction technique do not require experimental data from thermal conductivity measurements. The maximum error between extracted parameters extracted by proposed method and conventional method was about 14%, which is not a severe mismatch for real application. The proposed model is applicable to design of both for thermoelectric coolers and thermo electric generators.

• Journal of Sensor Science and Technology
• /
• v.24 no.5
• /
• pp.353-357
• /
• 2015

A new SPICE-compatible model for a gate/body-tied PMOSFET photodetector (GBT PD) with an overlapping control gate is presented. The proposed SPICE-compatible model of a GBT PD with an overlapping control gate makes it possible to control the photocurrent. Research into GBT PD modeling was proposed previously. However, the analysis and simulation of GBT PDs is not lacking. This SPICE model concurs with the measurement results, and it is simpler than previous models. The general GBT PD model is a hybrid device composed of a MOSFET, a lateral bipolar junction transistor (BJT), and a vertical BJT. Conventional SPICE models are based on complete depletion approximation, which is more applicable to reverse-biased p-n junctions; therefore, they are not appropriate for simulating circuits that are implemented with a GBT PD with an overlapping control gate. The GBT PD with an overlapping control gate can control the sensitivity of the photodetector. The proposed sensor is fabricated using a $0.35{\mu}m$ two-poly, four-metal standard complementary MOS (CMOS) process, and its characteristics are evaluated.