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http://dx.doi.org/10.6109/jicce.2016.14.2.115

General SPICE Modeling Procedure for Double-Gate Tunnel Field-Effect Transistors  

Najam, Syed Faraz (Department of Electronic and Computer Engineering, Faculty of Electrical Engineering, Universiti Teknologi Malaysia)
Tan, Michael Loong Peng (Department of Electronic and Computer Engineering, Faculty of Electrical Engineering, Universiti Teknologi Malaysia)
Yu, Yun Seop (Department of Electrical, Electronic, and Control Engineering and IITC, Hankyong National University)
Publication Information
Journal of information and communication convergence engineering / v.14, no.2, 2016 , pp. 115-121 More about this Journal
Abstract
Currently there is a lack of literature on SPICE-level models of double-gate (DG) tunnel field-effect transistors (TFETs). A DG TFET compact model is presented in this work that is used to develop a SPICE model for DG TFETs implemented with Verilog-A language. The compact modeling approach presented in this work integrates several issues in previously published compact models including ambiguity about the use of tunneling parameters Ak and Bk, and the use of a universal equation for calculating the surface potential of DG TFETs in all regimes of operation to deliver a general SPICE modeling procedure for DG TFETs. The SPICE model of DG TFET captures the drain current-gate voltage (Ids-Vgs) characteristics of DG TFET reasonably well and offers a definite computational advantage over TCAD. The general SPICE modeling procedure presented here could be used to develop SPICE models for any combination of structural parameters of DG TFETs.
Keywords
Compact model; Drain current; Inverter; Potential profile; TFET; Verilog;
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1 J. Wang, C. Wu. Q. Huang, C. Wang, and R. Huang, “A closedform capacitance model for tunnel FETs with explicit surface potential solutions,” Journal of Applied Physics, vol. 116, no. 9, article ID. 094501, 2014.
2 R. Vishnoi and M. J. Kumar, “Compact analytical model of dual material gate tunneling field-effect transistor using interband tunneling and channel transport,” IEEE Transactions on Electron Devices, vol. 61, no. 6, pp. 1936-1942, 2014.   DOI
3 J. Wan, C. Le Royer, A. Zaslavsky, and A. Cristoloveanu, “A tunneling field effect transistor model combining interband tunneling with channel transport,” Journal of Applied Physics, vol. 110, no. 10, article ID. 104503, 2011.   DOI
4 V. Prabhat and A. K. Dutta, “Analytical surface potential and drain current models of dual-metal-gate double-gate tunnel-FETs,” IEEE Transactions on Electron Devices, vol. 63, no. 5, pp. 2190-2196, 2016.   DOI
5 H. Xu, Y. Dai, N. Li, and J. Xu, “A 2-D semi-analytical model of double-gate tunnel field-effect transistor,” Journal of Semiconductors, vol. 36, no. 5, pp. 1-7, 2015.
6 ITRS report [Online], Available: http://www.itrs2.net/itrsreports.html.
7 Universal TFET model [Online], Available: https://nanohub.org/publications/31/1.
8 III-V Tunnel FET Model [Online], Available: https://nanohub.org/publications/12/2.
9 A. Khakifirooz, O. M. Nayfeh, and D. Antoniadis, “A simple semiempirical short-channel MOSFET current–voltage model continuous across all regions of operation and employing only physical parameters,” IEEE Transactions on Electron Devices, vol. 56, no. 8, pp. 1674-1680, 2009.   DOI
10 A. Biswas, L. De Michielis, A. Bazigos, and A. M. Ionescu, "Compact modeling of DG-Tunnel FET for Verilog-A implementation," in Proceeding of 2015 45th European Solid State Device Research Conference (ESSDERC), Graz, pp. 40-43, 2015.
11 C. Tanaka, K. Adachi, M. Fujimatsu, Y. Kondo, A. Hokazono, and S. Kawanaka, “Implementation of TFET SPICE model for ultra-low power circuit analysis,” IEEE Journal of the Electron Devices Society, 2016, http://dx.doi.org.10.1109/JEDS.2016.2550606.   DOI
12 M. G. Bardon, H. P. Neves, R. Puers, and C. Van Hoof, “Pseudo-two-dimensional model for double-gate tunnel FETs considering the junctions depletion regions,” IEEE Transactions on Electron Devices, vol. 57, no. 4, pp. 827-834, 2010.   DOI
13 SILVACO International, ATLAS II Framework (ver. 5.10.2.R), Santa Clara, CA, 2005.
14 L. Zhang, J. He, and M. Chan, "A compact model for double-gate tunneling field-effect-transistors and its implications on circuit behaviors," in Proceeding of 2012 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, pp. 1-4, 2012.
15 L. Zhang, X. Lin, J. He, and M. Chan, “An analytical charge model for double-gate tunnel FETs,” IEEE Transactions on Electron Devices, vol. 59, no. 12, pp. 3217-3223, 2012.   DOI
16 C. Wu, R. Huang, Q. Huang, C. Wang, J. Wang, and Y. Wang, “An analytical surface potential model accounting for the dualmodulation effects in tunnel FETs,” IEEE Transactions on Electron Devices, vol. 61, no. 8, pp. 2690-2696, 2014.   DOI
17 E. O. Kane, “Zener tunneling in semiconductors,” Journal of Physics and Chemistry of Solids, vol. 12, no. 2, pp. 181-188, 1960.   DOI
18 C. Wang, C. Wu, J. Wang, Q. Huang, and R. Huang, “Analytical current model of tunneling field-effect transistor considering the impacts of both gate and drain voltages on tunneling,” Science China Information Sciences, vol. 58, no. 2, pp. 1-8, 2015.
19 M. Gholizadeh and S. E. Hosseini, “A 2-D analytical model for double-gate tunnel FETs,” IEEE Transactions on Electron Devices, vol. 61, no. 5, pp. 1494-1500, 2014.   DOI