• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1993.11a
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• pp.29-34
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• 1993

In this paper, we used one-dimensional process simulator, SUPREM-II, and two-dimensional device simulator, MINIMOS 4.0 to extract optimal process parameter that can minimize degradation of device characteristics caused by process parameter variation in the case of short channel nMOSFET and pMOSFET device. From this simulation, we have derieved the relationship between process parameter and device characteristics. Here we have presented a method to extract process parameters from design trend curve(DTC) obtained by process and device simulations. We parameters to verify the validity of the DTC method. The experimental result of 0.8 $\mu\textrm{m}$ channel length devices that have been fabricated with optimal that reduces short channel effects, that is, good drain current-voltage characteristics, low body effects and threshold voltage of 1.0 V, high punchthrough and breakdown voltage of 12 V, low subthreshold swing(S.S) values of 105 mV/decade.

• Transactions of the Korean Society of Mechanical Engineers
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• v.17 no.2
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• pp.438-444
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• 1993

The circuit board of an electronic equipment were simulated with a vertical channel which had thermal blocks protruded from one of the channel walls. A rought front plate was made of a circuit board attached with short wires to simulate the back side of a printed circuit board. Natural convection experiments were carried out to study the effects of channel space and rough front plate and to find the suitable characteristic value after the fourth row. The effect of a rough front plate was negligble. There were negligible effects of the channel space on the first and second heaters. Heat transfer coefficients after the third row decreased as the channel space decreased. Heat transfer coefficients were almost constant for larger than 20 mm channel space. A characteristic length was suggested to non-dimensionalize Nu and Ra numbers in a vertical channel with protruded heaters. A correlation was obtained using the new characteristic lengths.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.6
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• pp.647-654
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• 2013

The design and analysis of analog circuit application on CMOS technology are a challenge in deep sub-micrometer process. This paper is a study on the performance value of Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with Gate Stack and the channel engineering Single Halo (SH), Double Halo (DH). Four different structures have been analysed keeping channel length constant. The short channel parameters and different sub-threshold analog figures of merit (FOMs) are analysed. This work extensively provides the device structures which may be applicable for high speed switching and low power consumption application.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.1-6
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• 2002

For an optimum device design of nano-scale SOI devices, this paper describes the short channel effects of multi-gate structures SOI MOSFETs such as double gate, triple gate and quadruple gate, as well as a new proposed Pi gate using computer simulation. The simulation has been performed with different channel doping concentrations, channel widths, silicon film thickness, and vertical gate extension depths of Pi gate. From the simulation results, it is found that Pi gate devices have a large margin in determination of doping concentrations, channel widths and film thickness comparing to double and triple gate devices because Pi gate devices offer a better short channel effects.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.1
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• pp.109-114
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• 2002

In this paper, we have presented the simulation results ah)ut threshold voltage for Si-based MOSFETs with channel length of nano scale. We simulated the Si-based n channel MOSFETs with gate lengths from 180 to 30 nm in accordance to the constant voltage scaling theory and the lateral scaling. These MOSFETs had the lightly doped drain(LDD) structure, which is used for the reduction of electric field magnitude and short channel effects at the drain region. The stronger electric field at this region is due to scaling down. We investigated and analyzed the threshold voltage of these devices. This analysis will provide insight into some applicable limitations at the ICs and used for basis data at VLSI.

• Korean Journal of Materials Research
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• v.18 no.5
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• pp.272-276
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• 2008

In submicron MOSFET devices, maintaining the ratio between the channel length (L) and the channel depth (D) at 3 : 1 or larger is known to be critical in preventing deleterious short-channel effects. In this study, n-type SOI-MOSFETs with a channel length of $0.1\;{\mu}m$ and a Si film thickness (channel depth) of $0.033\;{\mu}m$ (L : D = 3 : 1) were virtually fabricated using a TSUPREM-4 process simulator. To form functioning transistors on the very thin Si film, a protective layer of $0.08\;{\mu}m$-thick surface oxide was deposited prior to the source/drain ion implantation so as to dampen the speed of the incoming As ions. The p-type boron doping concentration of the Si film, in which the device channel is formed, was used as the key variable in the process simulation. The finished devices were electrically tested with a Medici device simulator. The result showed that, for a given channel doping concentration of $1.9{\sim}2.5\;{\times}\;10^{18}\;cm^{-3}$, the threshold voltage was $0.5{\sim}0.7\;V$, and the subthreshold swing was $70{\sim}80\;mV/dec$. These value ranges are all fairly reasonable and should form a 'magic region' in which SOI-MOSFETs run optimally.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.805-811
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• 2012

In this paper, movement of conduction path has been analyzed for electron distribution in the channel of double gate(DG) MOSFET. The analytical potential distribution model of Poisson equation, validated in previous researches, has been used to analyze transport characteristics. DGMOSFETs have the adventage to be able to reduce short channel effects due to improvement for controllability of current by two gate voltages. Since short channel effects have been occurred in subthreshold region including threshold region, the analysis of transport characteristics in subthreshold region is very important. Also transport characteristics have been influenced on the deviation of electron distribution and conduction path. In this study, the influence of electron distribution on conduction path has been analyzed according to intensity and distribution of doping and channel dimension.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.12
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• pp.2655-2661
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• 2009

In this paper, an accurate noise parameters for thermal noise modeling of short channel MOSFET is derived and extracted. Fukui model for calculating the noise parameters of a MOSFET is modified by considering effects of parasitic elements in short channel, and it is compared with conventional noise model equation. In addition, for obtaining the intrinsic noise sources of devices, noise parameters(minimum noise figure $F_{min}$, equivalent noise resistance $R_n$ optimized source admittance $Y_{opt}=G_{opt}+B_{opt}$) in submicron MOSFETs is extracted. With this extraction method, the intrinsic noise parameters of MOSFET without effects of probe pad and extrinsic parasitic elements from RF noise measurements can be directly obtained.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.10
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• pp.2305-2309
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• 2010

In this paper, the variations of threshold voltage characteristics for ratio of channel length and thickness have been alanyzed for DG(Double Gate)MOSFET having top gate and bottom gate. Since the DGMOSFET has two gates, it has advantages that contollability of gate for current is nearly twice and SCE(Short Channel Effects) shrinks in nano devices. The channel length and thickness in MOSFET determines device size and extensively influences on SCEs. The threshold voltage roll-off, one of the SCEs, is large with decreasing channel length. The threshold voltage roll-off and drain induced barrier lowing have been analyzed with various ratio of channel length and thickness for DGMOSFET in this study.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.765-767
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• 2010

In this paper, the variations of threshold voltage characteristics for ratio of channel length and thickness have been alanyzed for DG(Double Gate)MOSFET having top gate and bottom gate. Since the DGMOSFET has two gates, it has advantages that contollability of gate for current is nearly twice and SCE(Short Channel Effects) shrinks in nano devices. The channel length and thickness in MOSFET determines device size and extensively influences on SCEs. The threshold voltage roll-off, one of the SCEs, is large with decreasing channel length. The threshold voltage roll-off has been analyzed with various ratio of channel length and thickness for DGMOSFET in this study.