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Device Design Guideline for Nano-scale SOI MOSFETs  

Lee, Jae-Ki (Dept. of Electronic Communication, Gachongil College)
Yu, Chong-Gun (Dept. of Electronics Engineering, Univ. of Incheon)
Park, Jong-Tae (Dept. of Electronics Engineering, Univ. of Incheon)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.39, no.7, 2002 , pp. 1-6 More about this Journal
Abstract
For an optimum device design of nano-scale SOI devices, this paper describes the short channel effects of multi-gate structures SOI MOSFETs such as double gate, triple gate and quadruple gate, as well as a new proposed Pi gate using computer simulation. The simulation has been performed with different channel doping concentrations, channel widths, silicon film thickness, and vertical gate extension depths of Pi gate. From the simulation results, it is found that Pi gate devices have a large margin in determination of doping concentrations, channel widths and film thickness comparing to double and triple gate devices because Pi gate devices offer a better short channel effects.
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1 Jong Tae park, J. P. Colinge, and C. H. Diaz, 'Pi-gate SOI MOSFET,' IEEE Electron Device Lett. Vol. 22, pp. 405-406, 2001   DOI   ScienceOn
2 Jong Tae Park, C. A. colinge, and J. P.Colinge, 'Comparison of gate structure for short-cahnnel SOI MOSFETs,' Proc. IEEE SOI Conf. 2001   DOI
3 G. Chindalore, S. A. Hareland, S. Jallepalli, A. F. Tasch, C. M. Maziar, V. K. F. Chia, and S. Smith, 'Experimental determination of threshold voltage shift due to quantum mechanical effects in MOS electron and hole inversion layers,' IEEE Electron Device Lett. Vol. 18, pp. 206- 208, 1997   DOI   ScienceOn
4 E. Rauly, O. Potavin, F. Balestra, and C. Raynaud, 'On the suthreshold swing and short channel effects in single and double gate deep submicron SOI-MOSFETs,' Solid-State Electronics, Vol. 43, pp. 2033-2037, 1999   DOI   ScienceOn
5 C. P. Auth and J. D. Plummer, 'Scaling theory for cylindrical fully-depleted, surrounding-gate MOSFET's,' IEEE Electron Device Lett. Vol. 18, pp. 74-76, 1997   DOI   ScienceOn
6 D. Hisamoto, W. C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T. J. King, J. Bokor, and C. Hu, 'FinFET-a self-alinged double-gate MOSFET scalable to 20nm,' IEEE Trans. Electron Device, Vol. 47, pp. 2320-2324, 2000   DOI   ScienceOn
7 J. P. Colinge, M. H. Gao, A. Romano, H, Mase, and C. Claeys, 'Silicon-on-insulator gate-all-around device', Tech. Dig. of IEDM, pp. 595-598, 1990   DOI
8 J. P. Colinge, X. Baie, V. Bayot, E. Grivei, 'A silicon-on-insulator quantum wire', Solid-State Electronics, Vol. 39, pp. 49-51, 1996   DOI   ScienceOn
9 H. S. P. Wong, D. J. Frank and P. M. Salomen, 'Device degsign considerations for double gate, ground-plane, and single-gate ultra-thin SOI MOSFETs at the 25nm channel length generation', Tech. Dig. of IEDM, pp. 98-101, 1998