• Transactions on Electrical and Electronic Materials
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• v.17 no.4
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• pp.196-200
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• 2016

We have developed new electrostatic discharge (ESD) protection devices with, bidirectional flip chip transient voltage suppression. The devices differ in their epitaxial (epi) layers, which were grown by reduced pressure chemical vapor deposition (RPCVD). Their ESD properties were characterized using current-voltage (I-V), capacitance-voltage (C-V) measurement, and ESD analysis, including IEC61000-4-2, surge, and transmission line pulse (TLP) methods. Two BD-FCTVS diodes consisting of either a thick (12 μm) or thin (6 μm), n-Si epi layer showed the same reverse voltage of 8 V, very small reverse current level, and symmetric I-V and C-V curves. The damage found near the corner of the metal pads indicates that the size and shape of the radius governs their failure modes. The BD-FCTVS device made with a thin n- epi layer showed better performance than that made with a thick one in terms of enhancement of the features of ESD robustness, reliability, and protection capability. Therefore, this works confirms that the optimization of device parameters in conjunction with the doping concentration and thickness of epi layers be used to achieve high performance ESD properties.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.6
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• pp.431-435
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• 2010

In this paper, we investigated the dependence of device performance and hot carrier lifetime on the channel direction of PMOSFET. $I_{D.sat}$ vs. $I_{Off}$ characteristic of PMOSFET with <100> channel direction is greater than that with <110> channel direction because carrier mobility of <100> channel direction is greater than that of <110> channel direction. However, hot carrier lifetime for <110> channel direction is much lower than that with <110> channel due to the greater impact ionization rate in the <100> channel direction. Therefore, concurrent consideration of reliability characteristics and device performance is necessary for channel strain engineering of MOSFETs.

• Transactions on Electrical and Electronic Materials
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• v.11 no.1
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• pp.15-19
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• 2010

In this paper, we discuss design considerations for an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) with a lateral asymmetric channel (LAC) doping profile. We employed a $0.35\;{\mu}m$ standard complementary MOSFET process for fabrication of the devices. The gates to the LAC doping overlap lengths were 0.5, 1.0, and $1.5\;{\mu}m$. The drain current ($I_{ON}$), transconductance ($g_m$), substrate current ($i_{SUB}$), drain to source leakage current ($i_{OFF}$), and channel-hot-electron (CHE) reliability characteristics were taken into account for optimum device design. The LAC devices with shorter overlap lengths demonstrated improved $I_{ON}$ and $g_m$ characteristics. On the other hand, the LAC devices with longer overlap lengths demonstrated improved CHE degradation and $I_{OFF}$ characteristics.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.1
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• pp.1-11
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• 2004

A FinFET, a novel double-gate device structure is capable of scaling well into the nanoelectronics regime. High-performance CMOS FinFETs , fully depleted silicon-on-insulator (FDSOI) devices have been demonstrated down to 15 nm gate length and are relatively simple to fabricate, which can be scaled to gate length below 10 nm. In this paper, some of the key elements of these technologies are described including sub-lithographic pattering technology, raised source/drain for low series resistance, gate work-function engineering for threshold voltage adjustment as well as metal gate technology, channel roughness on carrier mobility, crystal orientation effect, reliability issues, process variation effects, and device scaling limit.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.191-197
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• 2016

In this paper, we investigated the hotcarrier injection (HCI) mechanism, one of the most important reliability issues, in 10 nm node Input/Output (I/O) bulk FinFET. The FinFET has much intensive HCI damage in Fin-bottom region, while the HCI damage for planar device has relatively uniform behavior. The local damage behavior in the FinFET is due to the geometrical characteristics. Also, the HCI is significantly affected by doping profile, which could change the worst HCI bias condition. This work suggested comprehensive understanding of HCI mechanisms and the guideline of doping profile in 10 nm node I/O bulk FinFET.

• Journal of KSNVE
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• v.9 no.6
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• pp.1227-1233
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• 1999

Modern technology depends on the reliability of extremely high technology equipments. In the production of semiconductor wafer, optical and electron microscopes, ion-beam, laser device must maintain their alignments within a nanometer. This equipment requires a vibration free environment to provide its proper function. Especially, lithography and inspection devices, which have sub-nanometer class high accuracy and resolution, have come to necessity for producing more improved giga and tera class semiconductor wafers. This high technology equipments require very strict environmental vibration standard, vibration criteria, in proportion to the accuracy of the manufacturing, inspecting devices. This paper deals with the structural dynamic design in high class semiconductor factory in order to be satisfied more strict vibration criteria for high sensitive equipment.

• Journal of the Semiconductor & Display Technology
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• v.18 no.2
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• pp.82-86
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• 2019

The reliability of 3D NAND flash memory cell is affected by the charge migration which can be divided into the vertical migration and the lateral migration. To clarify the difference of two migrations, the activation energy of the charge loss is extracted and compared in a conventional square device pattern and a new test pattern where the perimeter of the gate is exaggerated but the area is same. The charge loss is larger in the suggested test pattern and the activation energy is extracted to be 0.058 eV while the activation energy is 0.28 eV in the square pattern.

• Korean Journal of Metals and Materials
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• v.47 no.5
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• pp.311-315
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• 2009

2-dimensional (2D) dopant profiling in semiconductor device was carried out by electron holography and scanning capacitance microscopy methods with the same multi-layered p-n junction sample. The dopant profiles obtained from two methods are in good agreement with each other. It demonstrates that reliability of dopant profile measurement can be increased through precise comparison of 2D profiles obtained from various techniques.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.4
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• pp.25-29
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• 2016

The semiconductor industry has been developed mainly by micronization process due to many advantages of miniaturization of devices. Mass production of semiconductors of 10 nm class has been started recently, and it is expected that the technology generation of 5 nm & 7 nm technology will come. However, excessive linewidth reduction affects physical limits and device reliability. To solve these problems, new process technology development and new concept devices are being studied. In this review, we introduce the next generation technology and introduce the advanced research for the new concept device.

• Journal of the Semiconductor & Display Technology
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• v.19 no.2
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• pp.51-54
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• 2020

To develop gas-distinguishing sensor system, it is highly required to integrate multiple sensors for effective detection of a single targeted gas or mixture of gases. In addition, it is important to collect the reliable data from individual sensors into one integrated measuring device. Collecting the data of toxic gases on the spot should be done without inhalation. We suggest simple wirelessly running system for data collection that guarantees both reliability of data sources and safety. Here, we made a multi-gas measuring instrument(device) combined with Bluetooth module which provides a safe and precise big data accumulation system.