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L. Chang, Y.-K. Choi, D. Ha, P. Ranade, S. Xiong, J. Bokor, C. Hu, and T.-J. King, 'Extremely Scaled Silicon Nano-CMOS Devices, Proceedings of the IEEE, vol.91, p. 1860-1873, 2003.
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L. Chang, Y.-K. Choi, J. Kedzierski, N. Lindert, P. Xuan, J. Bokor, C. Hu, and T.-J. King, 'Moore's Law Lives on', IEEE Circuits & Devices, vol.19, p.35-42, 2003
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Y.-K. Choi, D. Ha, E. Snow, J. Bokor, and T.-J. King, 'Reliability Study of CMOS FinFETs', IEEE IEDM Technical Digest, p.177-180, 2003.
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J.-S. Lee, Y.-K. Choi, D. Ha, S. Balasubramanian, T.-J. King, J. Bokor, 'Hydrogen Annealing Effect on DC and Low Frequency Noise Characteristics in CMOS FinFETs', IEEE Electron Device Letters, vol.24, p.186-188, 2003.
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P. Ranade, Y.-K. Choi, D. Ha, A. Agarwal, M. Ameen and T.-J. King, 'Tunable Work Function Molybdenum Gate Technology for FDSOI-CMOS', IEEE IEDM Technical Digest , Technical Digest, p.363-365, 2002.
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Y.-K. Choi, L. Chang, P. Ranade, J.-S. Lee, D. Ha, S. Balasubramanian, A. Agarwal, M. Ameen, T.-J. King, J. Bokor, 'FinFET Process Refinements for Improved Mobility and Gate Work Function Engineering, IEEE IEDM Technical Digest, p.259-262, 2002.
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D. Ha, P. Ranade, Y.-K. Choi, J.-S. Lee, T.-J. King and C. Hu, 'Ultra-Thin Body Silicon-on-Insulator (UTB-SOI) MOSFET with Metal Gate Work-Function Engineering for sub-70 nm Technology Node', Extended Abstracts of the 2002 International Conference on Solid State Devices and Materials, p.782-783, 2002
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Y.-K. Choi, T.-J. King, C. Hu, 'A Spacer Patterning Technology for Nanoscale CMOS', IEEE Transactions on Electron Devices, vol.49, p.436-441, 2002.
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S. Tang , L. Chang, N. Lindert, Y.-K. Choi, W.-C. Lee, X. Huang, V. Subramanian, J. Bokor, T.-J. King, and C. Hu, 'FinFET: A Quasi-Planar Double-Gate MOSFET,'2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, pp. 118-119, 2001
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Y.-K. Choi, D. Ha, T.-J. King, C. Hu, 'Nanoscale ultrathin body PMOSFETs with raised selective germanium source/drain', IEEE Electron Device Letters, vol.22, p.447-448, 2001
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Y.-K. Choi, T.-J. King, C. Hu, 'Spacer FinFET : Nanoscale Double-Gate CMOS Technology for the Terabit Era', Solid-State Electronics, vol.46, p.1595-1601, 2002
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Y.-K. Choi, J. Zhu, J. Grunes, J. Bokor, and G.A. Somorjai, 'Fabrication of Sub--10nm Silicon Nanowire Arrays by Size Reduction Lithography', Journal of Physical Chemistry B, vol.107, p.3340-3343, 2003
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Y.-K. Choi, N. Lindert, P. Xuan, S. Tang, D. Ha, E. Anderson, T.-J. King, J. Bokor, C. Hu, 'Sub-20nm CMOS FinFET Technologies', IEEE IEDM Technical Digest, p.421-424, 2001.
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F.-L. Yang, H.-Y. Chen, F.-C. Chen, Y.-L. Chan, K.-N. Yang, C.-J. Chen, H.-J. Tao, Y.-K. Choi, M.-S. Liang, C. Hu, '35nm CMOS FinFETs', Symposium on VLSI Technology Technical Digest, p.104-105, 2002.
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L. Chang, S. Tang, T.-J. King, J. Bokor, and C. Hu, 'Gate-Length Scaling and Threshold Voltage Control of Double-Gate MOSFETs,' IEDM Technical Digest, p.719-722, 2000.
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