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http://dx.doi.org/10.6117/kmeps.2016.23.4.025

Development of Interconnect Process Technology for 5 nm Technology Nodes  

Choi, Eunmi (Department of Nano materials Science & Engineering, School of Integrative Engineering, Chung-Ang University)
Pyo, Sung Gyu (Department of Nano materials Science & Engineering, School of Integrative Engineering, Chung-Ang University)
Publication Information
Journal of the Microelectronics and Packaging Society / v.23, no.4, 2016 , pp. 25-29 More about this Journal
Abstract
The semiconductor industry has been developed mainly by micronization process due to many advantages of miniaturization of devices. Mass production of semiconductors of 10 nm class has been started recently, and it is expected that the technology generation of 5 nm & 7 nm technology will come. However, excessive linewidth reduction affects physical limits and device reliability. To solve these problems, new process technology development and new concept devices are being studied. In this review, we introduce the next generation technology and introduce the advanced research for the new concept device.
Keywords
5 nm & 7 nm technology; 3D integration; carbon semiconductor; air gap; Extreme ultraviolet;
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