• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.1
• /
• pp.47-55
• /
• 2005

This work describes an 8b 240 MS/s CMOS ADC as one of embedded core cells for high-performance displays requiring low power and small size at high speed. The proposed ADC uses externally connected pins only for analog inputs, digital outputs, and supplies. The ADC employs (1) a two-step pipelined architecture to optimize power and chip size at the target sampling frequency of 240 MHz, (2) advanced bootstrapping techniques to achieve high signal bandwidth in the input SHA, and (3) RC filter-based on-chip I/V references to improve noise performance with a power-off function added for portable applications. The prototype ADC is implemented in a 0.18 um CMOS and simultaneously integrated in a DVD system with dual-mode inputs. The measured DNL and INL are within 0.49 LSB and 0.69 LSB, respectively. The prototype ADC shows the SFDR of 53 dB for a 10 MHz input sinewave at 240 MS/s while maintaining the SNDR exceeding 38 dB and the SFDR exceeding 50 dB for input frequencies up to the Nyquist frequency at 240 MS/s. The ADC consumes, 104 mW at 240 MS/s and the active die area is 1.36 ㎟.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.5 s.335
• /
• pp.31-38
• /
• 2005

The architecture and the implementation details of a UTMI(USB2.0 Transceiver Macrocell Interface) compatible USB2.0 transceiver chip were presented. To confirm the validation of the incoming data in noisy channel environment, a squelch state detector and a current mode Schmitt-trigger circuit were proposed. A current mode output driver to transmit 480Mbps data on the USB cable was designed and an on-die termination(ODT) which is controlled by a replica bias circuit was presented. In the USB system using plesiochronous clocking, to compensate for the frequency difference between a transmitter and a receiver, a synchronizer using clock data recovery circuit and FIFO was designed. The USB cable was modeled as the lossy transmission line model(W model) for circuit simulation by using a network analyzer measurements. The USB2.0 PHY chip was implemented by using 0.25um CMOS process and test results were presented. The core area excluding the IO pads was $0.91{\times}1.82mm^2$. The power consumptions at the supply voltage of 2.5V were 245mW and 150mW for high-speed and full-speed operations, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.5 s.335
• /
• pp.55-62
• /
• 2005

In this paper, we propose an efficient symbol detection algorithm for space-frequency OFDM (SF-OFDM) transmit diversity scheme and present the implementation results of the SF-OFDM WLAN baseband processor with the proposed algorithm. When the number of sub-carriers in SF-OFDM scheme is small, the interference between adjacent sub-carriers may be generated. The proposed algorithm eliminates this interference in a parallel manner and obtains a considerable performance improvement over the conventional detection algorithm. The bit error rate (BER) performance of the proposed detection algorithm is evaluated by the simulation. In the case of 2 transmit and 2 receive antennas, at $BER=10^{-4}$ the proposed algorithm obtains about 3 dB gain over the conventional detection algorithm. The packet error rate (PER), link throughput, and coverage performance of the SF-OFDM WLAN with the proposed detection algorithm are also estimated. For the target throughput at $80\%$ of the peak data rate, the SF-OFDM WLAN achieves the average SNR gain of about 5.95 dB and the average coverage gain of 3.98 meter. The SF-OFDM WLAN baseband processor with the proposed algorithm was designed in a hardware description language and synthesized to gate-level circuits using 0.18um 1.8V CMOS standard cell library. With the division-free architecture, the total logic gate count for the processor is 945K. The real-time operation is verified and evaluated using a FPGA test system.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.12
• /
• pp.53-60
• /
• 2005

This work proposes a 10b 100 MS/s $1.4\;mm^2$ CMOS ADC for low-power multimedia applications. The proposed two-step pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The wide-band SHA employs a gate-bootstrapping circuit to handle both single-ended and differential inputs with 1.2 Vp-p at 10b accuracy while the second-stage flash ADC employs open-loop offset sampling techniques to achieve 6b resolution. A 3-D fully symmetrical layout reduces the capacitor and device mismatch of the first-stage MDAC. The low-noise references are integrated on chip with optional off-chip voltage references. The prototype 10b ADC implemented in a 0.18 um CMOS shows the maximum measured DNL and INL of 0.59 LSB and 0.77 LSB, respectively. The ADC demonstrates the SNDR of 54 dB, the SFDR of 62 dB, and the power dissipation of 56 mW at 100 MS/s.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.12 s.354
• /
• pp.15-22
• /
• 2006

In this paper, 1.8V 8-bit 500MSPS Low-power CMOS Digital-to-Analog Converter(DAC) for UWB(Ultra Wide Band) Communication Systeme is proposed. The architecture of the DAC is based on a current steering 6+2 full matrix type which has low glitch and high linearity. In order to achieve a high speed and good performance, a current cell with a high output impedance and wide swing output range is designed. Further a thermometer decoder with same delay time and low-power switching decoder for high efficiency performance are proposed. The proposed DAC was implemented with TSMC 0.18um 1-poly 6-metal N-well CMOS technology. The measured SFDR was 49dB when the output frequency was 50MHz at 500MS/s sampling frequency. The measured INL and DNL were 0.9LSB and 0.3LSB respectively. The DAC power dissipation was 20mW and the effective chip area was $0.63mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.12 s.354
• /
• pp.47-54
• /
• 2006

This work proposes a dual-channel 6b 1GS/s ADC for ultra wide-band communication system applications. The proposed ADC based on a 6b interpolated flash architecture employs wide-band open-loop track-and-hold amplifiers, comparators with a wide-range differential difference pre-amplifier, latches with reduced kickback noise, on-chip CMOS references, and digital bubble-code correction circuits to optimize power, chip area, and accuracy at 1GS/s. The ADC implemented in a 0.18um 1P6M CMOS technology shows a signal-to-noise-and-distortion ratio of 30dB and a spurious-free dynamic range of 39dB at 1GS/s. The measured differential and integral non-linearities of the prototype ADC are within 1.0LSB and 1.3LSB, respectively. The dual-channel ADC has an active area of $4.0mm^2$ and consumes 594mW at 1GS/s and 1.8V.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.49 no.2
• /
• pp.1-8
• /
• 2012

This paper presents the accelerometer which is a key component of TPMS(Tire Pressure Monitoring System). Generally a piezoresistive accelerometer has characteristics of lower cost, better linearity and better immunity about the environmnet noise than a capacitive one. Three types of piezoresistive accelerometers are degined and simulated using ANSYS program. The best one is a piezoresistive sensor which is supported by four beams located at the center of the edge of the mass after comparing the characteristics of resonant frequency of the three types. Considering the sensor size and a simulated maximum stress and maximum displacement, the length of beams is set as $200{\mu}m$. The size of a piezoresistive accelerometer is $3.0mm{\times}3.0mm{\times}0.4mm$. The sensor output is characterized by measuring the output characteristic depending on angle. As a result the offset voltage of the accelerometer is 43.2 mV and its sensitivity is $42.5{\mu}V/V/g$. The temperature bias drift is measured. The shock durability of the sensor is 1500g and the measuring range is 0 ~ 60 g.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.8
• /
• pp.62-71
• /
• 2001

This paper presents a design of the real-time digital image enhancement preprocessor for CMOS image sensor. CMOS image sensor offers various advantages while it provides lower-quality images than CCD does. In order to compensate for the physical limitation of CMOS sensor, the spatially adaptive contrast enhancement algorithm was incorporated into the preprocessor with color interpolation, gamma correction, and automatic exposure control. The efficient hardware architecture for the preprocessor is proposed and was simulated in VHDL. It is composed of about 19K logic gates, which is suitable for low-cost one-chip PC camera. The test system was implemented on Altera Flex EPF10KGC503-3 FPGA chip in real-time mode, and performed successfully.

• Korean Journal of Clinical Pharmacy
• /
• v.16 no.2
• /
• pp.101-106
• /
• 2006

The aim of the present study was to evaluate the bioequivalence of two talniflumate preparations. We used Somalgen tablet (Kun Wha Pharmaceutical Co., Korea.) as a reference drug for bioequivalence of Crimain tablet (Samjini Pharmaceutical Ind. Co., Korea), and performed this whole study according to the guidelines of Korea Food and Drug Administration (KFDA). Twenty four healthy male volunteers, $22.8{\pm}2.2$ years in age and $64.6{\pm}5.3\;kg$ in body weight, were divided into two groups and a randomized $2{\times}2$ cross-over study was employed. After one tablet containing 370 mg of talniflumate was orally administered, blood was taken at predetermined time intervals and the concentrations of talniflumate in plasma were determined using HPLC method with UV-detector. The analysis system was validated in specificity, accuracy, precision and linearity. These items of the analysis condition in this study conform to the guideline of KFDA. The pharmacokinetic parameters such as $AUC_t\;and\;C_{max}$ were calculated using the analysis condition we established and ANOVA test was utilized for the statistical analysis of the parameters using logarithmically transformed $AUC_t$ and Cmax. $Mean{\pm}SD$ of reference drug and test drug in $AUC_t\;and\;C_{max}$ value were $1.27{\pm}0.58\;({\mu}g/ml{\cdot}hr)\;and\;0.27{\pm}0.13\;({\mu}g/ml)$ and $1.14{\pm}0.46\;({\mu}g/ml{\cdot}hr)\;and\;0.26{\pm}0.10\;({\mu}g/ml)$ respectively. The 90% confidence intervals using logarithmically transformed data were within the acceptance range of log(0.8) to log (1.25) for $AUC_t\;and\;C_{max}$, respectively. These results indicate that Samjin talniflumate tablet is bioequivalent to reference drug, Somalgen tablet.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.4
• /
• pp.13-20
• /
• 2008

This paper describes the design of low power 12bit Digital-to-Analog Converter(D/A Converter) using Pseudo-Segmentation method which shows the conversion rate of 80MHz and the power supply of 1.8V with 0.18um CMOS n-well 1-poly 6-metal process for advanced wireless communication system. Pseudo-segmentation method used in binary decoder consists of simple parallel buffer is employed for low power because of simpler configuration than that of thermometer decoder. Also, using deglitch circuit and swing reduced drivel reduces a switching noise. The measurement results of the proposed low power 12bit 80MHz CMOS D/A Converter shows SFDR is 66.01dBc at sampling frequency 80MHz, input frequency 1MHz and ENOB is 10.67bit. Integral nonlinearity(INL) / Differential nonlinearity(DNL) have been measured ${\pm}1.6LSB/{\pm}1.2LSB$. Glich energy is measured $49pV{\cdot}s$. Power dissipation is 46.8mW at 80MHz(Maximum sampling frequency) at a 1.8V power supply.