Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Dual-Channel 6b 1GS/s 0.18um CMOS ADC for Ultra Wide-Band Communication Systems

초광대역 통신시스템 응용을 위한 이중채널 6b 1GS/s 0.18um CMOS ADC

  • Published : 2006.12.25
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Abstract

This work proposes a dual-channel 6b 1GS/s ADC for ultra wide-band communication system applications. The proposed ADC based on a 6b interpolated flash architecture employs wide-band open-loop track-and-hold amplifiers, comparators with a wide-range differential difference pre-amplifier, latches with reduced kickback noise, on-chip CMOS references, and digital bubble-code correction circuits to optimize power, chip area, and accuracy at 1GS/s. The ADC implemented in a 0.18um 1P6M CMOS technology shows a signal-to-noise-and-distortion ratio of 30dB and a spurious-free dynamic range of 39dB at 1GS/s. The measured differential and integral non-linearities of the prototype ADC are within 1.0LSB and 1.3LSB, respectively. The dual-channel ADC has an active area of $4.0mm^2$ and consumes 594mW at 1GS/s and 1.8V.

본 논문에서는 초광대역 통신시스템 응용을 위한 이중채널 6b 1GS/s A/D 변환기 (ADC)를 제안한다. 제안하는 ADC는 IGS/s의 신호처리속도에서 전력, 칩 면적 및 정확도를 최적화하기 위해 인터폴레이션 기반의 6b 플래시 ADC 회로로 구성되며, 입력 단에 광대역 열린 루프 구조의 트랙-앤-홀드 증폭기를 사용하였으며, 넓은 입력신호범위를 처리하기 위한 이중입력의 차동증폭기와 함께 래치 단에서의 통상적인 킥-백 잡음 최소화기법 등을 적용한 비교기를 제안하였다. 또한, CMOS 기준 전류 및 전압 발생기를 온-칩으로 집적하였으며, 디지털 출력에서는 새로운 버블 오차 교정회로를 제안하였다. 본 논문에서 제안하는 ADC는 0.18um 1P6M CMOS 공정으로 제작되었으며, 1GS/s의 동작속도에서 SNDR 및 SFDR은 각각 최대 30dB, 39dB를 보이며, 측정된 시제품 ADC의 DNL 및 INL은 각각 1.0LSB, 1.3LSB 수준을 보여준다. 제안하는 이중채널 ADC의 칩 면적은 $4.0mm^2$이며, 측정된 소모 전력은 1.8V 전원 전압 및 1GS/s 동작속도에서 594mW이다.

Keywords

References

  1. K. H. Yoon, S. K. Park, and W. C. Kim, 'A 6b 500 MSample/s CMOS flash ADC with a background interpolated auto-zeroing technique,' in ISSCC Dig. Tech Papers, Feb. 1999, pp, 326-327 https://doi.org/10.1109/ISSCC.1999.759274
  2. I. Mehr and D. Dalton, 'A 500-MSample/s, 6-bit nyquist-rate ADC for disk-drive read-channel applications,' IEEE J Solid-State Circuits, vol. 34, no. 7, pp. 912-920, July 1999 https://doi.org/10.1109/4.772405
  3. Y. Tarnba and K. Yarnakido, 'A CMOS 6b 500 MSample/s ADC for a hard disk drive read channel,' in ISSCC Dig. Tech Papers, Feb. 1999, pp. 324-325 https://doi.org/10.1109/ISSCC.1999.759272
  4. K. Nagaraj, D. A. Martin, M. Wolfe, R. Chattopadhyay, S. Pavan, J. Cancio, and T. R. Viswanathan, 'A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converter in a 0.25-um digital CMOS process,' IEEE J Solid-State Circuits, vol. 35, no. 12, pp. 1760-1768, Dec. 2000 https://doi.org/10.1109/4.890289
  5. K. Sushihara, H. Kimura, Y. Okamoto, K. Nishimura, and A. Matsuzawa, 'A 6b 800 MSample/s CMOS A/D converter,' in ISSCC Dig Tech Papers, Feb. 2000, pp. 428-429 https://doi.org/10.1109/ISSCC.2000.839845
  6. K. Uyttenhove, A. Marques, and M. Steyaert, 'A 6-bit 1 GHz Acquisition Speed CMOS Flash ADC with Digital Error Correction,' in Proc. CICC, May 2000, pp.249-252 https://doi.org/10.1109/CICC.2000.852659
  7. B. Yu and W. C. Black, Jr. 'A 900 MS/s 6b interleaved CMOS flash ADC,' in Proc. CICC, May 2001, pp.149-152 https://doi.org/10.1109/CICC.2001.929744
  8. M. Choi and A. A Abidi, 'A 6-b 1.3-Gsample/s A/D converter in 0.35-um CMOS,' IEEE J Solid-State Circuits, vol. 36, no. 12, pp. 1847-1858, Dec. 2001 https://doi.org/10.1109/4.972135
  9. P. C. S. Scholtens and M. Vertregt, 'A 6-b 1.6-Gsample/s flash ADC in 0.18-um CMOS using averaging termination,' IEEE J Solid-State Circuits, vol. 37, no. 12, pp. 1599-1609, Dec. 2002 https://doi.org/10.1109/JSSC.2002.804334
  10. X. Jiang, Z. Wang, and M. F. Chang, 'A 2GS/s 6b ADC in 0.18um CMOS,' in ISSCC Dig. Tech Papers, Feb. 2003, pp. 322-323, 497 https://doi.org/10.1109/ISSCC.2003.1234317
  11. K. Uyttenhove and M. S. J. Steyaert, 'A 1.8- V 6-bit 1.3-GHz flash ADC in 0.25-um CMOS,' IEEE J Solid-State Circuits, vol. 38, no. 7, pp. 1115-1122, July 2003 https://doi.org/10.1109/JSSC.2003.813244
  12. D. Draxelmayr, 'A 6b 600MHz 10mW ADC Array in Digital 90nm CMOS,' in ISSCC Dig Tech Papers, Feb. 2004, pp. 264-265 https://doi.org/10.1109/ISSCC.2004.1332695
  13. X. Jiang and M. F. Chang, 'A 1-GHz Signal Bandwidth 6-bit CMOS ADC With Power-Efficient Averaging,' IEEE J Solid-State Circuits, vol. 40, no. 2, pp. 532-535, Feb. 2005 https://doi.org/10.1109/JSSC.2004.841033
  14. T. Wakirnoto, Y. Akazawa, and S. Konaka, 'Si bipolar 2-GHz 6-bit flash A/D conversion LSI,' IEEE J Solid-State Circuits, vol. 23, no. 6, pp. 1345-1350, Dec. 1988 https://doi.org/10.1109/4.90030
  15. K. Poulton, K. L. Knudsen, J. J. Corcoran, Keh-Chung Wang, R. B. Nubling, R. L. Pierson, M.-C. F. Chang, R. M. Asbeck, and R. T. Huang, 'A 6-b, 4 GSa/s GaAs HBT ADC,' IEEE J Solid-State Circuits, vol. 30, no. 10, pp. 1109-1118, Oct. 1995 https://doi.org/10.1109/4.466071
  16. H. Hasegawa, M. Yotsuyanagi, M. Yamaguchi, and K. Sone, 'A 1.5V video-speed current-mode current-tree A/D converter,' in Symp. VISI Circuits Dig. Tech Papers, June 1994, pp. 17-18
  17. Y. Nishirna, D. Sane, K Amana, S. Matsuba, and A. Yukawa, 'An 8-bit 200Ms/s 500mW BiCMOS ADC,' in Proc. CICC, May 1995, pp. 207-210 https://doi.org/10.1109/CICC.1995.518169
  18. M. J. Choe and B. S. Song, 'An 8b 100MSample/s CMOS pipelined folding ADC,' in Symp. VISI Circuits Dig. Tech Papers, June 1999, pp. 81-82 https://doi.org/10.1109/VLSIC.1999.797243
  19. B. Nauta and A. G. W. Venes, 'A 70-MS/s 110-mW 8-b CMOS folding and interpolating A/D converter,' IEEE J Solid-State Circuits, vol. 30, no. 12, pp. 1302-1308, Dec. 1995 https://doi.org/10.1109/4.482155
  20. K. H. Yoon, J. H. Lee, D. K. Jeong, and W. C. Kim, 'An 8-b 125Ms/s CMOS folding ADC for gigabit ethernet LSI,' in Symp. VISI Circuits Dig. Tech Papers, May 2000, pp. 212-213
  21. S. Tsukamoto, T. Endo, and W. G. Schofield, 'A CMOS 6b 400 Msample/s ADC with error correction,' in ISSCC Dig. Tech Papers, Feb. 1998, pp. 152-153
  22. Y. J. Cho and S. H. Lee, 'An 11b 70-MHz 1.2-mm2 49-mW 0.18-um CMOS ADC with on-chip current/voltage references,' IEEE Trans. Circuits Syst. I, vol. 52, no. 10, pp. 1989-1995, Oct. 2005 https://doi.org/10.1109/TCSI.2005.853251
  23. C. Yang, G. Dehng, J. Hsu, and S. Liu, 'New dynamic flip-flops for high-speed dual-modulus prescaler', IEEE J Solid-State. Circuits, vol. 33, no. 10, pp.1568-1571, Oct. 1998 https://doi.org/10.1109/4.720406