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A 10b 100 MSample/s $1.4\;mm^2$ 56 mW 0.18 urn CMOS A/D Converter for Low-Power Multimedia Applications  

Min Byoung-Han (Dep. of Electronic Engineering and Interdisciplinary Program of Integrated Biotechnology, Sogang University)
Park Hee-Won (System IC Division, LG Electronics Co., Ltd)
Chae Hee-Sung (Dep. of Electronic Engineering and Interdisciplinary Program of Integrated Biotechnology, Sogang University)
Sa Doo-Hwan (Dep. of Electronic Engineering and Interdisciplinary Program of Integrated Biotechnology, Sogang University)
Lee Seung-Hoon (Dep. of Electronic Engineering and Interdisciplinary Program of Integrated Biotechnology, Sogang University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.42, no.12, 2005 , pp. 53-60 More about this Journal
Abstract
This work proposes a 10b 100 MS/s $1.4\;mm^2$ CMOS ADC for low-power multimedia applications. The proposed two-step pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The wide-band SHA employs a gate-bootstrapping circuit to handle both single-ended and differential inputs with 1.2 Vp-p at 10b accuracy while the second-stage flash ADC employs open-loop offset sampling techniques to achieve 6b resolution. A 3-D fully symmetrical layout reduces the capacitor and device mismatch of the first-stage MDAC. The low-noise references are integrated on chip with optional off-chip voltage references. The prototype 10b ADC implemented in a 0.18 um CMOS shows the maximum measured DNL and INL of 0.59 LSB and 0.77 LSB, respectively. The ADC demonstrates the SNDR of 54 dB, the SFDR of 62 dB, and the power dissipation of 56 mW at 100 MS/s.
Keywords
ADC; CMOS;
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Times Cited By KSCI : 1  (Citation Analysis)
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1 M. Yoshioka, M. Kudo, K. Gotoh, and Y. Watanabe, 'A 10b 125MS/s 40mW Pipelined ADC in 0.18um CMOS,' in ISSCC Dig. Tech. Papers, Feb. 2005, pp. 282-283
2 황성욱, 이승훈. '광대역 종합 통신망 응용을 위한 8b 52 MHz CMOS 서브레인징 A/D 변환기 설계,' 전기전자학회 논문지, 제2권, 제2호, pp. 144-150, 1998년 12월   과학기술학회마을
3 M. J. Kim, H. S. Yoon, Y. J. Lee, and S. H. Lee, 'An 11b 70MHz 1.2 $mm^2$ 49 mW 0.18um CMOS ADC with On-Chip Current/Voltage References,' in Proc. Eur. Solid-State Circuits Conf., Sep. 2002, pp. 463-466
4 H. C. Choi, S. B. You, H. Y. Lee, H. J. Park, and J. W. Kim, 'A Calibration-Free 3V 16b 500kS/s 6mW $0.5mm^2$ ADC with 0.13um CMOS,' in Symp. VISI Circuits Dig. Tech. Papers, June 2004, pp. 76-77
5 S. M. Yoo, T. H. Oh, J. w. Moon, S. H. Lee, and U. K. Moon, 'A 2.5V 10b 120 MSample/s CMOS Pipelined ADC with high SFDR,' in Proc. CICC, May 2002, pp. 23.2.1-23.2.4   DOI
6 A. M. Abo and P. R. Gray, 'A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital converter,' IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 599-606, May 1999   DOI   ScienceOn
7 M. Clara, A. Wiesbauer, and F. Kuttner, 'A 1.8V Fully Embedded 10b 160MS/s Two-Step ADC in 0.18um CMOS,' in Proc. CICC, May 2002, pp. 23.1.1-23.1.4
8 S. M. Yoo, J. B. Park, H. S. Yang, H. H. Bae, K. H. Moon, H. J. Park, S. H. Lee, and J. H. Kim, 'A 10b 150MS/s 123mW 0.18um CMOS Pipelined ADC,' in ISSCC Dig. Tech. Papers, Feb. 2003, pp. 326-327
9 S. Ray, P. Tadeparthy, S. S. Rath, D. B. Lavanmoorthy, C. P. S. Sujit, and S. Mathur, 'A Low Power 10 Bit 80 MSPS Pipelined ADC in Digital CMOS Process,' in Proc. IEEE Midwest Symp. Circuits and Systems, Aug. 2002, vol. 1, pp. 579-582
10 J. Li and U. K. Moon, 'A 1.8-V 67mW 10-bit 100MSPS Pipelined ADC using Time-Shifted CDS Technique,' in Proc. CICC, Sep. 2003, pp. 17.2.1-17.2.4   DOI
11 B. M. Min, P. Kim, D. Boisvert, and A. Aude, 'A 69mW 10b 80MS/s Pipelined CMOS ADC,' in ISSCC Dig. Tech. Papers, Feb. 2003, pp. 324-325   DOI
12 Y. I. Park, S. Karthikeyan, F. Tsay, and E. Bartolome, 'A low power 10 bit, 80 MS/s CMOS pipelined ADC at 1.8V power supply,' in Proc. IEEE Int Symp. Circuits and Systems, May 2001, vol. 1, pp. 580-583   DOI
13 Y. I. Park, S. Karthikeyan, F. Tsay, and E. Bartolome, 'A 10b100Msample/s CMOS Pipelined ADC with 1.8V Power Supply,' in ISSCC Dig. Tech. Papers, Feb. 2001, pp. 130-131   DOI
14 B. Vaz, J. Goes, and N. Paulino, 'A 1.5-V 10-b 50 MS/s Time-Interleaved Switched-Opamp Pipeline CMOS ADC with High Energy Efficiency,' in Symp. VLSI Circuits Dig. Tech. Papers, June 2004, pp. 432-435