• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2011년도 춘계학술대회 논문집
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• pp.179-182
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• 2011

• 마이크로전자및패키징학회지
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• 제19권1호
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• pp.17-24
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• 2012

Recently, flip chip interconnection has been increasingly used in microelectronic assemblies. The common Flip chip interconnection is formed by reflow of the solder bumps. Lead-Tin solders and Tin-based solders are most widely used for the solder bump materials. However, the flip chip interconnection using these solder materials cannot be applied to temperature-sensitive components since solder reflow is performed at relatively high temperature. Therefore the development of low temperature bonding technologies is required in these applications. A few bonding techniques at low temperature of $150^{\circ}C$ or below have been reported. They include the reflow soldering using low melting point solder bumps, the transient liquid phase bonding by inter-diffusion between two solders, and the bonding using low temperature curable adhesive. This paper reviews various low temperature bonding methods.

• Journal of Welding and Joining
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• 제19권3호
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• pp.311-316
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• 2001

This paper presents that the affecting factors to the solderability and initial reliability. It is the factor that the coefficient of thermal expansion between package and PCB(Printed Circuit Board), the quantity of solder paste and reflow condition, and Au thickness of the solder ball pad on polyimide tape. As the reflow soldering condition for 48 ${\mu}BGA$ is changed, it is estimated that the quantity of Au diffusion at eutectic Sn-Pb solder surface and initial bonding strength of eutectic Sn-Pb solder and lead free solder. It is the result that quantitative measurement of Au diffusion quantity is difficult, but the shear strength of eutectic Sn-Pb solder joint is 842 mN at first reflow and increases 879 mN at third reflow. The major failure mode in solder is judged solder fracture. So, Au diffusion quantity is more affected by reflow temperature than by the reflow times.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제54권7호
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• pp.315-318
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• 2005

The effect of plasma cleaning was examined on package delamination phenomena in the integrated circuit (IC) packaging process. Without plasma cleaning, delamination was observed for all three experimental treatments applied after the packaging step, which include bake of If, reflow, and bake of If followed by reflow However, no delamination was observed when the plasma cleaning was performed before and after the wire bonding step. Plasma cleaning was found to be a critical step to improve the reliability of the package by reducing the possibility of contact failure between die pad and bonding wire.

• 마이크로전자및패키징학회지
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• 제28권2호
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• pp.65-70
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• 2021

본 연구에서는 레이저 접합 공정을 이용하여 flame retardant-4 (FR-4) 인쇄회로기판 (printed circuit board, PCB)의 organic solderability preservative (OSP) 표면처리 된 Cu pad와 전자부품을 Sn-57Bi-1Ag 저온 솔더 페이스트로 접합을 한 후 접합부의 계면 특성과 기계적 특성에 대하여 보고 하였다. 레이저 접합 공정은 레이저 파워 및 시간 등을 다르게 진행하여 접합 공정 조건이 접합부의 계면 및 기계적 특성에 미치는 영향을 살펴보았다. 레이저 접합 공정의 산업적 적용을 위하여 산업적으로 많이 이용되고 있는 리플로우 접합 공정을 이용한 접합부의 특성과도 비교 하였다. 레이저 접합 공정 적용 결과 2, 3 s의 짧은 공정 시간에도 계면에 Cu₆Sn₅ 금속간화합물 (intermetallic compound, IMC)를 생성하여 접합부를 안정적으로 형성함을 확인 하였다. 또한, 리플로우 공정과 비교해 보았을 때 레이저 접합 공정을 적용할 경우 접합부의 보이드 형성이 억제됨을 확인할 수 있었으며 접합부의 전단강도도 리플로우 공정 접합부보다 높은 기계적 강도를 나타냈다. 따라서, 레이저 접합 공정을 적용할 경우 짧은 접합 공정 시간에도 불구하고 안정적인 접합부 형성 및 높은 기계적 강도를 확보할 수 있는 것으로 기대된다.

• 한국정밀공학회지
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• 제31권10호
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• pp.865-871
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• 2014

Paradigm shift to 3-D chip stacking in electronic packaging has induced a lot of integration challenges due to the reduction in wafer thickness and pitch size. This study presents a hybrid bonding technology by self-alignment effect in order to improve the flip chip bonding accuracy with ultra-thin wafer. Optimization of Cu pillar bump formation and evaluation of various factors on self-alignment effect was performed. As a result, highly-improved bonding accuracy of thin wafer with a $50{\mu}m$ of thickness was achieved without solder bridging or bump misalignment by applying reflow process after thermo-compression bonding process. Reflow process caused the inherently-misaligned micro-bump to be aligned due to the interface tension between Si die and solder bump. Control of solder bump volume with respect to the chip dimension was the critical factor for self-alignment effect. This study indicated that bump design for 3D packaging could be tuned for the improvement of micro-bonding quality.

• 대한금속재료학회지
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• 제47권4호
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• pp.261-266
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• 2009

The mechanical and electrical properties of ball grid array (BGA) solder joints were measured, consisting of Sn-3.5Ag, with organic solderability preservative (OSP)-finished Cu pads and Electroless Nickel/Immersion Gold (ENIG) surface finishes. The mechanical properties were measured by die shear test. When ENIG PCB was upper joint and OSP PCB was lower joint, the highest shear force showed at the third reflow. When OSP PCB was upper joint and ENIG PCB was lower joint, the highest shear force showed at the forth reflow. For both joints, after the die shear results reached the highest shear force, shear force decreased as a function of increasing reflow number. Electrical property of the solder joint decreased with the function of increasing reflow number. The scanning electron microscope results show that the IMC thickness at the bonding interface gets thicker while the number of reflow increases.

• 마이크로전자및패키징학회지
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• 제21권1호
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• pp.1-6
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• 2014

고출력 LED 패키지의 열적 경로(thermal path)를 줄이기 위해 플립칩 본딩법에 대한 연구가 활발히 진행되고 있다. 본 연구에서는 Au-Sn 열압착 본딩 및 Sn-Ag-Cu(SAC) 리플로우 본딩을 이용하여 본딩 특성 및 열적특성을 비교 평가 하였다. Au-Sn 열압착 본딩은 50 N에서 $300^{\circ}C$의 접합온도로 본딩하였고, SAC 솔더는 솔더페이스트를 인쇄한 후 리플로우법으로 피크온도 $255^{\circ}C$에서 30 sec에서 본딩하였다. SAC 솔더를 사용한 LED 패키지의 전단강도는 $5798.5gf/mm^2$로 Au-Sn 열압착 본딩의 $3508.5gf/mm^2$에 비해 1.6배 높았다. 파단면과 단면분석 결과 Au-Sn, SAC 솔더 모두 LED 칩 내부에서 파단이 일어나는 것을 관찰하였다. 반면 Au-Sn 열압착 본딩 샘플의 열저항은 SAC솔더 접합 샘플에 비해 낮았으며, SAC 솔더 접합부 내부의 기공에 의해 열저항이 커짐을 알 수 있었다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 기술심포지움 논문집
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• pp.103-105
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• 2003

COG (Chip on Glass) technology using solder bump reflow has been investigated to attach IC chip directly on glass substrate of LCD panel. As It chip and LCD panel have to be heated to reflow temperature of the so]der bumps for COG bonding, it is necessary to use low-temperature solders to prevent the damage of liquid crystals of LCD panel. In this study, using the Sn-52In solder bumps of $40{\mu}m$ pitch size, solder joints between Si chip and glass substrate were made at temperature below $150^{\circ}C$. The contact resistance of the solder joint was $8.58m\Omega$, which was much lower than that of the joint made using the conventional ACF bonding technique. The Sn-52In solder joints with underfill showed excellent reliability at a hot humid environment.

• 반도체디스플레이기술학회지
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• 제22권4호
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• pp.38-47
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• 2023

Three dimensional (3D) packaging is a next-generation packaging technology that vertically stacks chips such as memory devices. The necessity of 3D packaging is driven by the increasing demand for smaller, high-performance electronic devices (HPC, AI, HBM). Also, it facilitates innovative applications across another fields. With growing demand for high-performance devices, companies of semiconductor fields are trying advanced packaging techniques, including 2.5D and 3D packaging, MR-MUF, and hybrid bonding. These techniques are essential for achieving higher chip integration, but challenges in mass production and fine-pitch bump connectivity persist. Advanced bonding technologies are important for advancing the semiconductor industry. In this review, it was described 3D packaging technologies for chip integration including mass reflow, thermal compression bonding, laser assisted bonding, hybrid bonding.