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http://dx.doi.org/10.7736/KSPE.2014.31.10.865

Micro-bump Joining Technology for 3 Dimensional Chip Stacking  

Ko, Young-Ki (Micro-joining center, Korea Institute of Industrial Technology)
Ko, Yong-Ho (Micro-joining center, Korea Institute of Industrial Technology)
Lee, Chang-Woo (Micro-joining center, Korea Institute of Industrial Technology)
Publication Information
Journal of the Korean Society for Precision Engineering / v.31, no.10, 2014 , pp. 865-871 More about this Journal
Abstract
Paradigm shift to 3-D chip stacking in electronic packaging has induced a lot of integration challenges due to the reduction in wafer thickness and pitch size. This study presents a hybrid bonding technology by self-alignment effect in order to improve the flip chip bonding accuracy with ultra-thin wafer. Optimization of Cu pillar bump formation and evaluation of various factors on self-alignment effect was performed. As a result, highly-improved bonding accuracy of thin wafer with a $50{\mu}m$ of thickness was achieved without solder bridging or bump misalignment by applying reflow process after thermo-compression bonding process. Reflow process caused the inherently-misaligned micro-bump to be aligned due to the interface tension between Si die and solder bump. Control of solder bump volume with respect to the chip dimension was the critical factor for self-alignment effect. This study indicated that bump design for 3D packaging could be tuned for the improvement of micro-bonding quality.
Keywords
3D packaging; TSV (Through Silicon Via); Micro-bump; Stacking; Thin wafer;
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