• Proceedings of the Korean Society of Precision Engineering Conference
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• 2011.06a
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• pp.179-182
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• 2011

• Journal of the Microelectronics and Packaging Society
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• v.19 no.1
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• pp.17-24
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• 2012

Recently, flip chip interconnection has been increasingly used in microelectronic assemblies. The common Flip chip interconnection is formed by reflow of the solder bumps. Lead-Tin solders and Tin-based solders are most widely used for the solder bump materials. However, the flip chip interconnection using these solder materials cannot be applied to temperature-sensitive components since solder reflow is performed at relatively high temperature. Therefore the development of low temperature bonding technologies is required in these applications. A few bonding techniques at low temperature of $150^{\circ}C$ or below have been reported. They include the reflow soldering using low melting point solder bumps, the transient liquid phase bonding by inter-diffusion between two solders, and the bonding using low temperature curable adhesive. This paper reviews various low temperature bonding methods.

• Journal of Welding and Joining
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• v.19 no.3
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• pp.311-316
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• 2001

This paper presents that the affecting factors to the solderability and initial reliability. It is the factor that the coefficient of thermal expansion between package and PCB(Printed Circuit Board), the quantity of solder paste and reflow condition, and Au thickness of the solder ball pad on polyimide tape. As the reflow soldering condition for 48 ${\mu}BGA$ is changed, it is estimated that the quantity of Au diffusion at eutectic Sn-Pb solder surface and initial bonding strength of eutectic Sn-Pb solder and lead free solder. It is the result that quantitative measurement of Au diffusion quantity is difficult, but the shear strength of eutectic Sn-Pb solder joint is 842 mN at first reflow and increases 879 mN at third reflow. The major failure mode in solder is judged solder fracture. So, Au diffusion quantity is more affected by reflow temperature than by the reflow times.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.54 no.7
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• pp.315-318
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• 2005

The effect of plasma cleaning was examined on package delamination phenomena in the integrated circuit (IC) packaging process. Without plasma cleaning, delamination was observed for all three experimental treatments applied after the packaging step, which include bake of If, reflow, and bake of If followed by reflow However, no delamination was observed when the plasma cleaning was performed before and after the wire bonding step. Plasma cleaning was found to be a critical step to improve the reliability of the package by reducing the possibility of contact failure between die pad and bonding wire.

• Journal of the Microelectronics and Packaging Society
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• v.28 no.2
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• pp.65-70
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• 2021

In this study, interfacial properties and mechanical properties of joints were reported after Cu pads finished with organic solderability preservative (OSP) on flame retardant-4 (FR-4) printed circuit board (PCB) and electronic components were joined with a Sn-57Bi-1Ag solder paste by using a laser bonding process. The laser bonding process was performed under various bonding conditions with changing a laser power and a bonding time and effects of bonding conditions on interfacial and mechanical properties of joints were analyzed. In order to apply for industry, properties of bonding joints using a reflow bonding process which are widely used were compared. When the laser bonding process were performed, we observed that Cu₆Sn₅ intermetallic compounds (IMCs) were fully formed at the interface although the bonding times were very short about 2 and 3 s. Furthermore, void formations of the joints by using the laser bonding process were suppressed at the joints with comparing to the reflow bonding process and shear strengths of bonding joints were higher than that by using the reflow bonding process. Therefore, in spite of a very short bonding time, it is expected that joints will be stably formed and have a high mechanical strength by using the laser bonding process.

• Journal of the Korean Society for Precision Engineering
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• v.31 no.10
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• pp.865-871
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• 2014

Paradigm shift to 3-D chip stacking in electronic packaging has induced a lot of integration challenges due to the reduction in wafer thickness and pitch size. This study presents a hybrid bonding technology by self-alignment effect in order to improve the flip chip bonding accuracy with ultra-thin wafer. Optimization of Cu pillar bump formation and evaluation of various factors on self-alignment effect was performed. As a result, highly-improved bonding accuracy of thin wafer with a $50{\mu}m$ of thickness was achieved without solder bridging or bump misalignment by applying reflow process after thermo-compression bonding process. Reflow process caused the inherently-misaligned micro-bump to be aligned due to the interface tension between Si die and solder bump. Control of solder bump volume with respect to the chip dimension was the critical factor for self-alignment effect. This study indicated that bump design for 3D packaging could be tuned for the improvement of micro-bonding quality.

• Korean Journal of Metals and Materials
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• v.47 no.4
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• pp.261-266
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• 2009

The mechanical and electrical properties of ball grid array (BGA) solder joints were measured, consisting of Sn-3.5Ag, with organic solderability preservative (OSP)-finished Cu pads and Electroless Nickel/Immersion Gold (ENIG) surface finishes. The mechanical properties were measured by die shear test. When ENIG PCB was upper joint and OSP PCB was lower joint, the highest shear force showed at the third reflow. When OSP PCB was upper joint and ENIG PCB was lower joint, the highest shear force showed at the forth reflow. For both joints, after the die shear results reached the highest shear force, shear force decreased as a function of increasing reflow number. Electrical property of the solder joint decreased with the function of increasing reflow number. The scanning electron microscope results show that the IMC thickness at the bonding interface gets thicker while the number of reflow increases.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.1
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• pp.1-6
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• 2014

Flip chip bonded LED packages possess lower thermal resistance than wire bonded LED packages because of short thermal path. In this study, thermal and bonding properties of flip chip bonded high brightness LED were evaluated for Au-Sn thermo-compression bonded LEDs and Sn-Ag-Cu reflow bonded LEDs. For the Au-Sn thermo-compression bonding, bonding pressure and bonding temperature were 50 N and 300oC, respectively. For the SAC solder reflow bonding, peak temperature was $255^{\circ}C$ for 30 sec. The shear strength of the Au-Sn thermo-compression joint was $3508.5gf/mm^2$ and that of the SAC reflow joint was 5798.5 gf/mm. After the shear test, the fracture occurred at the isolation layer in the LED chip for both Au-Sn and SAC joints. Thermal resistance of Au-Sn sample was lower than that of SAC bonded sample due to the void formation in the SAC solder.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.103-105
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• 2003

COG (Chip on Glass) technology using solder bump reflow has been investigated to attach IC chip directly on glass substrate of LCD panel. As It chip and LCD panel have to be heated to reflow temperature of the so]der bumps for COG bonding, it is necessary to use low-temperature solders to prevent the damage of liquid crystals of LCD panel. In this study, using the Sn-52In solder bumps of $40{\mu}m$ pitch size, solder joints between Si chip and glass substrate were made at temperature below $150^{\circ}C$. The contact resistance of the solder joint was $8.58m\Omega$, which was much lower than that of the joint made using the conventional ACF bonding technique. The Sn-52In solder joints with underfill showed excellent reliability at a hot humid environment.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.38-47
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• 2023

Three dimensional (3D) packaging is a next-generation packaging technology that vertically stacks chips such as memory devices. The necessity of 3D packaging is driven by the increasing demand for smaller, high-performance electronic devices (HPC, AI, HBM). Also, it facilitates innovative applications across another fields. With growing demand for high-performance devices, companies of semiconductor fields are trying advanced packaging techniques, including 2.5D and 3D packaging, MR-MUF, and hybrid bonding. These techniques are essential for achieving higher chip integration, but challenges in mass production and fine-pitch bump connectivity persist. Advanced bonding technologies are important for advancing the semiconductor industry. In this review, it was described 3D packaging technologies for chip integration including mass reflow, thermal compression bonding, laser assisted bonding, hybrid bonding.