• 전기의세계
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• 제20권2호
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• pp.9-14
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• 1971

N type single crystal CdTe is grown by doping Gallium as 0.01 percent, by using zone melting method. And also p type CdTe is grown by doping Ag, Sb, and Te as 0.01%. Resistivity and Concentration of the n.p type single crystal are measured. And then Li ions are implanted on the n type CdTe by high voltage accellerator with different amount of impurity. Indium is evaporated on the p type in high vacuum condition. These sample are heated so as to make P-N Junction in Argon gas flow. Electrical properties for solar cell are investigated. Photovoltage and current are found to be varyed according to following factor: 1) amount of impurity 2) diffusion thickness 3) temperature and time for making P-N junction. Efficiency of the P-N Junction evaporated Indium is 6.5 when it is heated at 380.deg. C for 15 minutie.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제55권2호
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• pp.72-75
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• 2006

A CMOS compatible Super Junction LDMOS (SJ-LDMOS) structure, which reduces substrate-assisted depletion effects, is reported. The proposed structure uses a N-buffer layer between the pillars and P-substrate to achieve global charge balance between the pillars, the N-buffer layer and the P-substrate. The new structure features high breakdown voltage, low on-resistance, and reduced sensitivity to doping imbalance in the pillars.

• 전자공학회논문지A
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• 제29A권8호
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• pp.71-77
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• 1992

According to increasing the doping concentration in p-n junction, a tunneling current through trap as well as SRH(Shockley-Read-Hall) generation-recombination current in depletion region occurs. It is the tunneling current that is a dominant current at the forward bias. In this paper, the new tunneling-recombination equation is derived. The thermal generation-recombination current and tunneling current though trap can be easily calculated at the same time because this equation has the same form as the SRH generation-recombination equation. For the validity of this equation, 2 kind of samples are simulated. The one is $n^{+}$-p junction device fabricated with MCT(Mercury Cadmium Telluride, mole fraction=0.29), the other Si n$^{+}-p^{+}$ junction. From the results for MCT $n^{+}$-p junction device and comparing the simulated and expermental I-V characteristics for Si n$^{+}-p^{+}$ junction, it is shown that this equation is a good description for tunneling through trap and thermal generation-recombination current calculation.

• 대한전자공학회논문지SD
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• 제41권1호
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• pp.9-14
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• 2004

본 논문에서는 Si의 유효 이온화 계수를 온도 함수로 추출하였고, 이 유효 이온화 계수를 이용하여 Si $p^+n$ 접합에서의 항복 전압을 위한 해석적 표현식을 온도 함수로 유도하였다. 100K 300K 및 500K일 경우, 해석적 항복 전압 결과는 $10^{14}cm^{-3}{\~} 10^{17}cm^{-3}$의 농도 범위에서 실험 결과 및 시뮬레이션 결과와 비교하여 오차 범위 $3\%$ 이내로 잘 일치하였다.

• 동력기계공학회지
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• 제4권4호
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• pp.99-107
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• 2000

In this study several P type and N type ceramic semiconductors were prepared by atomic valence control and their electric resistivities were investigated with various concentrations of additive impurities. N-P junctions were made by thin film printing method and their varistor-like characteristics were investigated and their availability was discussed. The results are followings, 1) Some N type semiconductors with a proper concentration of additive impurity have minimum resistivities. 2) The N-P junction samples with ZnO as a constituent material of N type semiconductor have linearity in voltage-current characteristics, but the other N-P junction samples have the non-linearity, 3) Some N-P junction samples showed the good varistor-like characteristics.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권1호
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• pp.43-51
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• 2006

80-nm self-aligned n-and p-channel I-MOS devices were demonstrated by using a novel fabrication method featuring double sidewall spacer, elevated drain structure and RTA process. The fabricated devices showed a normal transistor operation with extremely small subthreshold swing less than 12.2 mV/dec at room temperature. The n- and p-channel I-MOS devices had an ON/OFF current of 394.1/0.3 ${\mu}A$ and 355.4/8.9 ${\mu}A$ per ${\mu}m$, respectively. We also investigated some critical issues in device design such as the junction depth of the source extension region and the substrate doping concentration.

• 한국진공학회지
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• 제19권5호
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• pp.391-396
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• 2010

실리콘 태양전지의 pn 접합 계면특성을 조사하기 위해서 p형 실리콘 기판 위에 전기로를 이용한 $POCl_3$ 공정을 통하여 n형의 불순물을 주입하여 pn 접합을 만들었다. n형 불순물의 확산되어 들어가는 공정시간이 길고 공정온도가 높을수록 면저항은 줄어들었다. n형 불순물의 주입이 많아질수록 pn 접합 계면에서의 전자친화도가 줄어들면서 면저항은 감소되었다. 면저항이 줄어든 이유는 pn 접합계면에서 전자홀쌍이 생성되면서 이동길이가 길어지고 재결합률이 감소하였기 때문이다. n형의 불순물 확산공정시간이 긴 태양전지 셀에서 F.F. 계수가 높게 나타났으며, 효율도 높게 나타났다.

• 대한전자공학회논문지
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• 제24권2호
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• pp.260-264
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• 1987

Gaussian $n^{+}$-p집합에 대해 위치함수인 유전율을 고려한 Poisson's equation의 일반적인 형태를 수치적으로 풀어 접합깊이가 전하밀도에 미치는 영향을 살펴 보았다. 또한 유전율의 변화에 기인한 전하 쌍극자의 해석적인 모델을 제시하였다.

• 한국전기전자재료학회논문지
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• 제30권6호
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• pp.372-375
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• 2017

ZnO thin films were deposited by RF magnetron sputtering and then diffused by using an As source in the ampouletube. Also, the ZnO p-n homojunction was made by using As-doped ZnO thin films, and its properties were analyzed. After the As doping, the surface roughness increased, the crystal quality deteriorated, and the full width at half maximum was increased. The As-doped ZnO thin films showed typical p-type properties, and their resistivity was as low as $2.19{\times}10^{-3}{\Omega}cm$, probably because of the in-diffusion from an external As source and out-diffusion from the GaAs substrate. Also, the ZnO p-n junction displayed the typical rectification properties of a p-n junction. Therefore, the As diffusion method is effective for obtaining ZnO films with p-type properties.

• 대한전자공학회논문지SD
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• 제42권10호
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• pp.9-18
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• 2005

Si, GaAs, InP 및 $In_{0.53}Ga_{0.47}AS$ 계단형 $p^{+}n$ 접합에서의 항복전압을 위한 해석적 표현식을 유도하였다. 해석적 항복전압을 위해 각 물질에 대한 Marsland의 lucky drift 파라미터를 이용하여 유효이온화계수를 각각 추출하였고, 이의 이온화 적분을 통해 얻은 해석적 항복전압 결과는 $10^{14}cm\;^{-3}\~5\times10\;^{17}cm\;^{-3}$도핑 농도 범위에서 실험 결과와 $10\%$ 오차 범위 이내로 잘 일치하였다.