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Super Junction LDMOS with N-Buffer Layer  

Park Il-Yong (토론토대 전기 및 컴퓨터공학과)
Publication Information
The Transactions of the Korean Institute of Electrical Engineers C / v.55, no.2, 2006 , pp. 72-75 More about this Journal
Abstract
A CMOS compatible Super Junction LDMOS (SJ-LDMOS) structure, which reduces substrate-assisted depletion effects, is reported. The proposed structure uses a N-buffer layer between the pillars and P-substrate to achieve global charge balance between the pillars, the N-buffer layer and the P-substrate. The new structure features high breakdown voltage, low on-resistance, and reduced sensitivity to doping imbalance in the pillars.
Keywords
N-Buffer Layer; LDMOS; Super Junction;
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