JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

Characterization and Design Consideration of 80-nm Self-Aligned N-/P-Channel I-MOS Devices

  • Choi, Woo-Young (Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering, Seoul National University) ;
  • Lee, Jong-Duk (Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering, Seoul National University) ;
  • Park, Byung-Gook (Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering, Seoul National University)
  • Published : 2006.03.31
Download PDF
⟨ Previous Next ⟩

Abstract

80-nm self-aligned n-and p-channel I-MOS devices were demonstrated by using a novel fabrication method featuring double sidewall spacer, elevated drain structure and RTA process. The fabricated devices showed a normal transistor operation with extremely small subthreshold swing less than 12.2 mV/dec at room temperature. The n- and p-channel I-MOS devices had an ON/OFF current of 394.1/0.3 ${\mu}A$ and 355.4/8.9 ${\mu}A$ per ${\mu}m$, respectively. We also investigated some critical issues in device design such as the junction depth of the source extension region and the substrate doping concentration.

Keywords

References

  1. D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H.-S. P. Wong, 'Device scaling limits of Si MOSFETs and their application dependencies,' Proc. IEEE, vol. 89, pp. 259-288, Mar. 2001 https://doi.org/10.1109/5.915374
  2. M. Lundstrom, 'Device physics at the scaling limit: what matters?' in IEEE Int. Electron Devices (IEDM) Tech. Dig., pp. 789-792, 2003
  3. S. Borkar, 'Circuit techniques for subthreshold leakage avoidance, control, and tolerance,' in IEEE Int. Electron Devices (IEDM) Tech. Dig., pp. 421-424, 2004 https://doi.org/10.1109/IEDM.2004.1419176
  4. K. Gopalakrishnan, P. B. Griffin, and J. D. Plummer, 'I-MOS: a novel semiconductor device with a subthreshold slope lower than kT/q,' in IEEE Int. Electron Devices (IEDM) Tech. Dig., pp. 289-292, 2002 https://doi.org/10.1109/IEDM.2002.1175835
  5. W. Y. Choi, J. Y. Song, J. D. Lee, Y. J. Park, and B.-G. Park, 'A novel biasing scheme for I-MOS (impact-ionization MOS) devices,' IEEE Trans. Nanotechnology, vol. 4, no. 3, pp. 322-325, May 2005 https://doi.org/10.1109/TNANO.2005.847001
  6. W. Y. Choi, B. Y. Choi, D.-S. Woo, J. D. Lee, and B.-G. Park, 'A new fabrication method for selfaligned nanoscale I-MOS (Impact-ionization MOS),' in 62nd Annual Device Research Conference, pp. 211-212, 2004 https://doi.org/10.1109/DRC.2004.1367869
  7. W. Y. Choi, J. Y. Song, J. D. Lee, Y. J. Park, and B.-G. Park, '100-nm n-/p-channel I-MOS using a novel self-aligned structure,' IEEE Electron Device Lett., vol. 26, no. 4, pp. 261-263, Apr. 2005 https://doi.org/10.1109/LED.2005.844695
  8. A. Hokazono, K. Ohuchi, K. Miyano, I. Mizushima, Y. Tsunashima, and Y. Toyoshima, 'Source/drain engineering for sub-100nm CMOS using selective epitaxial growth technique,' in IEEE Int. Electron Devices (IEDM) Tech. Dig., pp.243-246, 2000 https://doi.org/10.1109/IEDM.2000.904302
  9. G. Gibbons, and J. Kocsis, 'Breakdown voltages of germanium plane-cylindrical junctions,' IEEE Trans. Electron Devices, vol. 12, pp. 193-198, Apr. 1965 https://doi.org/10.1109/T-ED.1965.15477
  10. R. S. Muller, and T. I. Kamins, Device electronics for integrated circuits, New York: John Willey & Sons, 1986
  11. D. P. Kennedy, and R. R. O'Brien, 'Avalanche breakdown calculations for a planar p-n junction,' IBM Journal of Research and Development, vol. 10, no. 3, pp. 213-219, May 1966 https://doi.org/10.1147/rd.103.0213
  12. W. Y. Choi, H. Kim, B. Lee, J. D. Lee, and B.-G. Park, 'Stable threshold voltage extraction using Tikhonov's regularization theory,' IEEE Trans. Electron Devices, vol. 51, no. 11, pp. 1833-1839, Nov. 2004 https://doi.org/10.1109/TED.2004.837010
  13. H.-S. Wong, M. H. White, T. J. Krutsick, and R. V. Booth, 'Modeling of transconductance degradation and extraction of threshold voltage in thin oxide MOSFETs,' Solid-State Electronics, vol.30, no.9, pp.953-968, 1987 https://doi.org/10.1016/0038-1101(87)90132-8