• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.174-174
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• 2008

Non-volatile memories using ferroelectric-gate field-effect transistors (Fe-FETs) with a metal/ferroelectric/semiconductor gate stack (MFS-FETs) make non-destructive read operation possible. In addition, they also have features such as high switching speed, non-volatility, radiation tolerance, and high density. However, the interface reaction between ferroelectric materials and Si substrates, i.e. generation of mobile ions and short retention, make it difficult to obtain a good ferroelectric/Si interface in an MFS-FET's gate. To overcome these difficulties, Fe-FETs with a metal/ferroelectric/insulator/semiconductor gate stack (MFIS-FETs) have been proposed, where insulator as a buffer layer is inserted between ferroelectric materials and Si substrates. We prepared $SrBi_2Ta_2O_9$ (SBT) film as a ferroelectric layer and $LaZrO_x$ (LZO) film as a buffer layer on p-type (100) silicon wafer for making the MFIS-FET devices. For definition of source and drain region, phosphosilicate glass (PSG) thin film was used as a doping source of phosphorus (P). Ultimately, the n-channel ferroelectric-gate FET using the SBT/LZO/Si Structure is fabricated. To examine the ferroelectric effect of the fabricated Fe-FETs, drain current ($I_d$) versus gate voltage ($V_g$) characteristics in logarithmic scale was measured. Also, drain current ($I_d$) versus drain voltage ($V_d$) characteristics of the fabricated SBT/LZO/Si MFIS-FETs was measured according to the gate voltage variation.

• 한국전기전자재료학회논문지
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• 제37권1호
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• pp.48-55
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• 2024

The changes in threshold voltage and DIBL were investigated for changes in remanent polarization P_r and coercive field E_c, which determine the characteristics of the P-E hysteresis curve of ferroelectric in NCFET (negative capacitance FET). The threshold voltage and DIBL (drain-induced barrier lowering) were observed for a junctionless double gate MOSFET using a gate oxide structure of MFMIS (metal-ferroelectric-metal-insulator-semiconductor). To obtain the threshold voltage, series-type potential distribution and second derivative method were used. As a result, it can be seen that the threshold voltage increases when P_r decreases and E_c increases, and the threshold voltage is also maintained constant when the P_r/E_c is constant. However, as the drain voltage increases, the threshold voltage changes significantly according to P_r/E_c, so the DIBL greatly changes for P_r/E_c. In other words, when P_r/E_c=15 pF/cm, DIBL showed a negative value regardless of the channel length under the conditions of ferroelectric thickness of 10 nm and SiO₂ thickness of 1 nm. The DIBL value was in the negative or positive range for the channel length when the P_r/E_c is 25 pF/cm or more under the same conditions, so the condition of DIBL=0 could be obtained. As such, the optimal condition to reduce short channel effects can be obtained since the threshold voltage and DIBL can be adjusted according to the device dimension of NCFET and the P_r and E_c of ferroelectric.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권1호
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• pp.16-21
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• 2006

A simple doping method to fabricate a very thin channel body of the p-type FinFETs with a 20 nm gate length by solid-phase-diffusion (SPD) process was developed. Using the poly-boron-films (PBF) as a novel diffusion source of boron and the rapid thermal annealing (RTA), the p-type sourcedrain extensions of the FinFET devices with a threedimensional structure were doped. The junction properties of boron doped regions were investigated by using the $p^+-n$ junction diodes which showed excellent electrical characteristics. Single channel and multi-channel p-type FinFET devices with a gate length of 20-100 nm was fabricated by boron diffusion process using PBF and revealed superior device scalability.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1992년도 춘계학술대회 논문집
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• pp.86-90
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• 1992

We have studied the characteristics of n-and p-channel FETs with submicron channel length fabricated by twin-well process. Threshold voltage variation and potential distribution with channel ion implantation conditions and impurity profile of n-and p-channel region wee simulated using SUPREM-II and MINIMOS 4.0 simulater, P-channel FET had buried-channel in the depth of 0.15 $\mu\textrm{m}$ from surface by counter-doped boron ion implantation for threshold voltage adjustment. As a result of device measurement, we have obtained good drain saturation characteristics for 3.3 [V] opreation, minimized short channel effect with threshold voltage shift below 0.2[V], high punchthrough and breakdown voltage above 10[V] and low subthreshold value.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권3호
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• pp.224-236
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• 2013

This work presents a comparative study of four Double Gate tunnel FET (DG-TFET) architectures: conventional p-i-n DG-TFET, p-n-p-n DG-TFET, a gate dielectric engineered Heterogate (HG) p-i-n DG-TFET and a new device architecture with the merits of both Hetero Gate and p-n-p-n, i.e. HG p-n-p-n DG-TFET. It has been shown that, the problem of high gate capacitance along with low ON current for a p-i-n TFET, which severely hampers the circuit performance of TFET can be overcome by using a p-n-p-n TFET with a dielectric engineered Hetero-gate architecture (i.e. HG p-n-p-n). P-n-p-n architecture improves the ON current and the heterogeneous dielectric helps in reducing the gate capacitance and suppressing the ambipolar behavior. Moreover, the HG architecture does not degrade the output characteristics, unlike the gate drain underlap architecture, and effectively reduces the gate capacitance.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.517-518
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• 2008

Highly integrated ISFETs require the monolithic implementation of ISFETs, CMOS electronics, and additional sensors on the same chip This paper presents novel packaging type of CMOS ISFET pH sensor using standard CMOS FET chip and extended sensing membrane which is separated from CMOS FET. This proposed packaging type will make it easy to fabricate CMOS ISFET pH sensors

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권2호
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• pp.68-73
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• 2006

We propose a damascene gate FinFET with Si nanocrystals implemented on bulk silicon wafer for low voltage flash memory device. The use of optimized SRON (Silicon-Rich Oxynitride) process allows a high degree of control of the Si excess in the oxide. The FinFET with Si nanocrystals shows high program/erase (P/E) speed, large $V_{TH}$ shifts over 2.5V at 12V/$10{\mu}s$ for program and -12V/1ms for erase, good retention time, and acceptable endurance characteristics. Si nanocrystal memory with damascene gate FinFET is a solution of gate stack and voltage scaling for future generations of flash memory device. Index Terms-FinFET, Si-nanocrystal, SRON(Si-Rich Oxynitride), flash memory device.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.66-66
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• 2010

$SnO_2$ 나노선은 n-type 반도체 특성을 띄며 트랜지스터, 가스 센서, pH 센서 등 여러 분야에 걸쳐 다양하게 사용되고 있다. $SnO_2$ 나노선은 그 자체만으로 시계방향의 전기적 히스테리시스를 보이며 이것은 나노선 표면에 흡착된 물이나 산소가 발생시키는 전자 갇힘 현상이 가장 큰 원인으로 작용한다. 특히 고분자를 게이트 절연막으로 사용할 경우 게이트 절연막의 전기적 히스테리시스가 소자 특성에 영향을 미치게 되며, 고분자 절연막의 히스테리시스는 $SnO_2$ 나노선의 히스테리시스와 반대인 반시계 방향의 특성을 보인다. 고분자 내에서 발생하는 히스테리시스는 고분자 사이에 흡착된 물 분자나 고분자의 높은 극성을 가지는 작용기 등이 원인으로 작용한다. 전기적 히스테리시스는 FET소자를 구동하는데 있어 부적절한 특성으로, 이것의 원인을 이해하는 것은 중요하며 히스테리시스의 방향과 크기를 조절할 수 있는 기술 또한 중요하다. 본 연구에서는 폴리이미드(PMDA-ODA)를 게이트 절연막으로 사용하여 플렉시블 기판을 만들고 그 위에 $SnO_2$ 나노선을 슬라이딩 전이 방식으로 정렬하여 플렉시블 FET를 제작하였다. 제작된 소자는 $0.7cm\;{\times}\;0.7cm$ 넓이 안에 300개의 FET가 존재하며 SEM 이미지를 통해 넓이 $50{\mu}m$, 길이 $5{\mu}m$의 FET채널에 약 150개의 나노선이 연결되어 있는 것을 확인했다. 이 소자의 히스테리시스는 폴리이미드의 교차결합 정도에 따라, 그리고 폴리이미드 절연막을 제작할 때의 습도에 따라 변하게 된다. 교차결합이 많아지고 습도가 낮아질수록 폴리이미드 절연막 내부에 흡착되는 물분자가 줄어들게 되고 절연막의 히스테리시스가 사라지며 시계방향의 나노선 히스테리시스가 지배적이 된다. 반대로 교차결합이 줄어들고 습도가 높아질수록 폴리이미드 절연막 내부에 물분자가 늘어 나면서 시계반대방향의 폴리이미드 히스테리시스가 FET의 전기적 특성에서 눈에 띄게 나타난다. 이 실험을 통해 고분자 절연막을 사용한 $SnO_2$ 나노선 FET의 전기적 히스테리시스를 조절할 수 있었으며, 소자의 히스테리시스를 없앨 수 있는 가능성에 대해서 논하고자 한다.

• The Journal of Korean Physical Therapy
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• 제16권1호
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• pp.32-48
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• 2004

The purpose of this study was to evaluate the change of functional ambulation profile(FAP) and temporal-spatial gait parameters in hemiplegic patient by forceful respiratory exercise. 28 Hemiplegic patients due to stroke was randomized in 3 groups, forceful expiratory training(FET), forceful inspiratory training(FIT) and control group. In the experimental groups, ordinary physical therapy with forceful expiratory training and forceful inspiratory training for 20 minutes duration 3 times per week for 6 weeks were respectively performed. In the control group, only ordinary physical therapy was done. FAP and temporal-spatial gait parameters was measured at before and after experiments. The results of this experimental study were as follows : 1. In comparison of FAP before and after experiment, the FAP was significantly increased in the FET and FIT group (p<.01). In comparison of difference of FAP among 3 groups, there was the significant difference between the FIT group and the control group (p<.05). 2. The results of temporal-spatial gait parameters are as follows : 1) In comparison of gait velocity before and after experiment, the gait velocity was significantly increased in the FET and FIT group (p<.05). In comparison of difference of the gait velocity among 3 groups, there was the significantly difference between the FIT group and the control group (p<.05). 2) In comparison of gait cadence before and after experiment, the gait cadence was significantly increased in FIT group (p<.05). In comparison of the difference of the gait cadence among 3 groups, there was no significant difference between the FIT group and the control group (p>.05). Based on these results, it is concluded that the forced respiratory exercise program for 6 weeks can be improve the FAP and temporal-spatial gait parameters in hemiplegic patients. Therefore, the forced respiratory exercise is useful to improve the walking ability in hemiplegic patients.

• 한국전기전자재료학회논문지
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• 제30권9호
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• pp.589-595
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• 2017

MOS-FET structured gas sensors were manufactured using MWCNTs for application as NOx gas sensors. As the gas sensors need to be heated to facilitate desorption of the gas molecules, heat dispersion plays a key role in boosting the degree of uniformity of molecular desorption. We report the desorption of gas molecules from the sensor at $150^{\circ}C$ for different sensor electrode gaps (30, 60, and $90{\mu}m$). The COMSOL analysis program was used to verify the process of heat dispersion. For heat analysis, structure of FET gas sensor modeling was proceeded. In addition, a property value of the material was used for two-dimensional modeling. To ascertain the degree of heat dispersion by FEM, the governing equations were presented as partial differential equations. The heat analysis revealed that although a large electrode gap is advantageous for effective gas adsorption, consideration of the heat dispersion gradient indicated that the optimal electrode gap for the sensor is $60{\mu}m$.