Characteristics of N-and P-Channel FETs Fabricated with Twin-Well Structure

Twin-well 구조로 제작된 N채널 및 P채널 FET의 특성

We have studied the characteristics of n-and p-channel FETs with submicron channel length fabricated by twin-well process. Threshold voltage variation and potential distribution with channel ion implantation conditions and impurity profile of n-and p-channel region wee simulated using SUPREM-II and MINIMOS 4.0 simulater, P-channel FET had buried-channel in the depth of 0.15 $\mu\textrm{m}$ from surface by counter-doped boron ion implantation for threshold voltage adjustment. As a result of device measurement, we have obtained good drain saturation characteristics for 3.3 [V] opreation, minimized short channel effect with threshold voltage shift below 0.2[V], high punchthrough and breakdown voltage above 10[V] and low subthreshold value.