• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1996년도 추계학술대회 논문집
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• pp.13-17
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• 1996

Superthin ONO ( oxide -nitride - oxide ) structures were fabricated for the MONOS nonvolatile memory device with a 20$\AA$ tunneling oxide, 40$\AA$ nitride and 40$\AA$ blocking oxide. The compositions of each layer in a superthin ONO structure were investigated. Also, the characteristics of trap related to the memory quality were examined.

• 한국전기전자재료학회논문지
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• 제24권9호
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• pp.693-696
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• 2011

Recently, amorphous oxide semiconductors (AOSs) based thin-film transistors (TFTs) have received considerable attention for application in the next generation displays industry. The research trends of AOSs based TFTs investigation have focused on the high device performance. The electrical properties of the TFTs are influenced by trap density. In particular, the threshold voltage ($V_{th}$) and subthreshold swing (SS) essentially depend on the semiconductor/gate-insulator interface trap. In this article, we investigated the effects of Ar plasma-treated $SiO_2$ insulator on the interfacial property and the device performances of amorphous indium gallium zinc oxide (a-IGZO) TFTs. We report on the improvement in interfacial characteristics between a-IGZO channel layer and gate insulator depending on Ar power in plasma process, since the change of treatment power could result in different plasma damage on the interface.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2008년도 추계종합학술대회 B
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• pp.604-607
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• 2008

본 연구에서는 NAND 플래시메모리를 위한 기본 셀로서 p채널 SONOS (silicon-oxide-nitride-oxide-silicon) 트랜지스터를 제작하고 이것의 메모리특성을 조사하였다. SONOS 트랜지스터의 제작은 $0.13{\mu}m$ low power용 standard logic 공정기술을 사용하였다. 게이트 절연막의 두께는 터널 산화막 $20{\AA}$, 질화막 $14{\AA}$, 그리고 블로킹산화막의 두께는 $49{\AA}$이다. 제작된 SONOS 트랜지스터는 낮은 쓰기/지우기 전압, 빠른 지우기 속도, 그리고 비교적 우수한 기억유지특성과 endurance 특성을 나타내었다.

• 전기전자학회논문지
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• 제25권4호
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• pp.770-773
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• 2021

본 논문에서는 tapering과 ferroelectric(HfO₂)구조가 적용된 3D NAND flash memory의 프로그램 이후 시간경과에 따른 retention특징을 분석했다. Nitride에 trap된 전자는 시간이 지남에 따라 lateral charge migration이 발생한다. 프로그램 이후 시간이 지남에 따라 trap된 전자가 tapering에 의해 두꺼워진 채널 쪽으로 lateral charge migration이 더 많이 발생하는 것을 확인했다. 또한 Oxide-Nitride-Ferroelectric (ONF) 구조는 polarization에 의해 lateral charge migration이 완화되기 때문에 기존 Oxide-Nitride-Oxide (ONO) 구조 보다 문턱전압(V_th)의 변화량이 줄어든다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권2호
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• pp.82-87
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• 2007

The electrical properties of metallic junction diodes and metallic source/drain (S/D) Schottky barrier metal-oxide-semiconductor field-effect transistor (SB-MOSFET) were simulated. By using the abrupt metallic junction at the S/D region, the short-channel effects in nano-scaled MOSFET devices can be effectively suppressed. Particularly, the effects of trap states at the metal-silicide/silicon interface of S/D junction were simulated by taking into account the tail distributions and the Gaussian distributions at the silicon band edge and at the silicon midgap, respectively. As a result of device simulation, the reduction of interfacial trap states with Gaussian distribution is more important than that of interfacial trap states with tail distribution for improving the metallic junction diodes and SB-MOSFET. It is that a forming gas annealing after silicide formation significantly improved the electrical properties of metallic junction devices.

• 한국전기전자재료학회논문지
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• 제24권11호
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• pp.900-904
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• 2011

In this paper, we investigated an anomalous hump phenomenon under the positive bias stress in p-type LTPS TFTs. The devices with inferior electrical performance also show larger hump phenomenon. which can be explained by the sub-channel induced from trapped electrons under thinner gate oxide region. We can confirm that the devices with larger hump have larger interface trap density ($D_{it}$) and grain boundary trap density ($N_{trap}$) extracted by low-high frequency capacitance method and Levinson-Proano method, respectively. From the C-V with I-V transfer characteristics, the trapped electrons causing hump seem to be generated particularly from the S/D and gate overlapped region. Based on these analysis, the major cause of an anomalous hump phenomenon under the positive bias stress in p-type poly-Si TFTs is explained by the GIDL occurring in the S/D and gate overlapped region and the traps existing in the channel edge region where the gate oxide becomes thinner, which can be inferred by the fact that the magnitude of the hump is dependent on the average trap densities.

• 한국전기전자재료학회논문지
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• 제27권10호
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• pp.648-652
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• 2014

We have investigated the effect of electrical properties of amorphous InGaZnO thin film transistors (a-IGZO TFTs) by post thermal annealing in $O_2$ ambient. The post-annealed in $O_2$ ambient a-IGZOTFT is found to be more stable to be used for oxide-based TFT devices, and has better performance, such as the on/off current ratios, sub-threshold voltage gate swing, and, as well as reasonable threshold voltage, than others do. The interface trap density is controlled to achieve the optimum value of TFT transfer and output characteristics. The device performance is significantly affected by adjusting the annealing condition. This effect is closely related with the modulation annealing method by reducing the localized trapping carriers and defect centers at the interface or in the channel layer.

• 한국전기전자재료학회논문지
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• 제22권2호
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• pp.101-106
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• 2009

In this paper, Thin films of $HfO_2$/Hf were deposited on p-type wafer by Atomic Layer Deposition (ALD). We studied the electrical and material characteristics of $HfO_2$/Hf/Si MOS capacitor depending on thickness of Hf metal layer. $HfO_2$ films were deposited using TEMAH and $O_3$ at $350^{\circ}C$. Samples were then annealed using furnace heating to $500^{\circ}C$. Round-type MOS capacitors have been fabricated on Si substrates with $2000\;{\AA}$-thick Pt top electrodes. The composition rate of the dielectric material was analyzed using TEM (Transmission Electron Microscopy), XRD (X-ray Diffraction) and XPS (X-ray Photoelectron Spectroscopy). Also the capacitance-voltage (C-V), conductance-voltage (G-V), and current-voltage (I-V) characteristics were measured. We calculated the density of oxide trap charges and interface trap charges in our MOS device. At the interface between $HfO_2$ and Si, both Hf-Si and Hf-Si-O bonds were observed, instead of Si-O bond. The sandwiched Hf metal layer suppressed the growing of $SiO_x$ layer so that $HfSi_xO_y$ layer was achieved. And finally, the generation of both oxide trap charge and interface trap charge in $HfO_2$ film was reduced effectively by using Hf metal layer.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1998년도 추계학술대회 논문집
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• pp.9-12
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• 1998

Film characteristics of thin reoxidized nitrided oxides were investigated by SIMS analysis and C-V method in order to use the gate dielectric for charge-trap type NVSMs instead of ONO stacked layers. Nitric oxide(NO) annealed film has the nitrogen content sharply peaked at the Si-SiO$_2$ interface, while it is broad for nitrous oxide($N_2$O) ambient. The nitrogen peak concentration increased with anneal temperature and time. The position of nitrogen content in the oxide layer was due to be precisely controlled. For the films annealed NO ambient at 80$0^{\circ}C$ for 30min. followed by reoxidized at 85$0^{\circ}C$, the maximum memory window of 3.5V was obtained and the program condition was +12V, 1msec for write and -l3V, 1msec for erase.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.257-257
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• 2011

The amorphous indium-gallium-zinc-oxide (a-IGZO) materials for use in high performance display research fields are strongly investigated due to its good performance, such as high mobility and better transparency. However, the stability of a-IGZO materials is increasingly becoming one of critical issues due to the sub-gap electron trap sites induced by rough interfaces during deposition processing. It is well-known that the threshold voltage shift is related to interface roughness and oxygen vacancy formed by breaking weak chemical bonds. Here, we report the better properties of transparent oxide transistors by reducing the threshold voltage shift with an external rf plasma supported magnetron sputtering system. Mainly, our sputtering method causes the surface of sample to be sleek, so that it prevents the formation of various defects, such as shallow electron trap sites in the interface. External rf power was applied from 0 to 50W during RF sputtering process to enhance the stability of our oxide transistor without having a large voltage shift. To observe the effects of external rf-plasma source on the properties of our devices, Scanning Electron Microscopy (SEM), Atomic Force Microscopy (AFM), Transmission Electron Microscopy (TEM) are carried out to observe surface roughness and morphology of sputtered thin film. In addition, typical electrical properties, such as I-V characteristics are analyzed.