• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.1
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• pp.50-57
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• 1986

The fabricatoin sequence of GaAs MIS type diode and its electrical characteristics are presented. Used wafers were undoped GaAS wafer adn Te-doped GaAs wafer. Au and AuGe/Ni was used as schottky contact metal and ohmic contact metal respectively. Oxide layer on GaAs surface was formed by water vapor saturated oxide growth technique and dry oxidation technique. In Te-doped GaAs wafer, cutin voltage of MIS type diode was enhanced about 3V comparing with non-oxide layer diode. From light I-V characteristics fill factor of MIS type Te-doped GaAs diode was about 64%, Voc(open circuit voltage) was 0.67V.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.8
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• pp.587-592
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• 2010

We have fabricated schottky barrier diode (SBDs) using polar (c-plane) and non polar (a-, m-plane) n-type 6H-SiC wafers. Ni/SiC ohmic contact was accomplished on the backside of the SiC wafers by thermal evaporation and annealed for 20minutes at $950^{\circ}C$ in mixture gas ($N_2$ 90% + $H_2$ balanced). The specific contact resistance was $3.6{\times}10^{-4}{\Omega}cm^2$ after annealing at $950^{\circ}C$. The XRD results of the alloyed contact layer show that formation of $NiSi_2$ layer might be responsible for the ohmic contact. The active rectifying electrode was formed by the same thermal evaporation of Ni thin film on topside of the SiC wafers and annealed for 5 minutes at $500^{\circ}C$ in mixture gas ($N_2$ 90% + $H_2$ balanced). The electrical properties of SBDs have been characterized by means of I-V and C-V curves. The forward voltage drop is about 0.95 V, 0.8 V and 0.8 V for c-, a- and m-plane SiC SBDs respectively. The ideality factor (${\eta}$) of all SBDs have been calculated from log(I)-V plot. The values of ideality factor were 1.46, 1.46 and 1.61 for c-, a- and m-plane SiC SBDs, respectively. The schottky barrier height (SBH) of all SBDs have been calculated from C-V curve. The values of SBH were 1.37 eV, 1.09 eV and 1.02 eV for c-, a- and m-plane SiC SBDs, respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.9
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• pp.818-824
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• 2006

The effects of high-temperature process required to fabricate the SiC devices on the surface morphology and the electrical characteristics were investigated for 4H-SiC Schottky diodes. The 4H-SiC diodes without a graphite cap layer as a protection layer showed catastrophic increase in an excess current at a forward bias and a leakage current at a reverse bias after high-temperature annealing process. Moreover it seemed to deviate from the conventional Schottky characteristics and to operate as an ohmic contact at the low bias regime. However, the 4H-SiC diodes with the graphite cap still exhibited their good electrical characteristics in spite of a slight increase in the leakage current. Therefore, we found that the graphite cap layer serves well as the protection layer of silicon carbide surface during high-temperature annealing. Based on a closer analysis on electric characteristics, a conductive surface transfiguration layer was suspected to form on the surface of diodes without the graphite cap layer during high-temperature annealing. After removing the surface transfiguration layer using ICP-RIE, Schottky diode without the graphite cap layer and having poor electrical characteristics showed a dramatic improvement in its characteristics including the ideality factor[${\eta}$] of 1.23, the schottky barrier height[${\Phi}$] of 1.39 eV, and the leakage current of $7.75\{times}10^{-8}\;A/cm^{2}$ at the reverse bias of -10 V.

• Journal of Sensor Science and Technology
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• v.10 no.4
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• pp.207-213
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• 2001

A Schottky type GaN ultraviolet photodetector with a mesa structure was fabricated by depositing an Al ohmic contact on an $n^+$-GaN layer and a Pt Schottky contact on a GaN layer. The undoped GaN(0.5um)/$n^-$-GaN(0.1 um)/$n^+$-GaN(1.5 um) multi-layer structure was grown on a sapphire substrate using MOCVD. The Schottky contact properties were characterized for different passivation conditions. The leakage current of the fabricated Schottky diode was 2 nA at a reverse voltage of 5V. Plus the photocurrent was 120uA using a hydrargyrum lamp with an optical power of 1mW at a wavelength of 365 nm. The diode exhibited an ultraviolet-visible rejection ratio of $10^2$.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.4
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• pp.159-163
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• 2003

ln this work, we studied electrical characteristics and leakage current mechanism of $Ta_2O_{5}$ MOS(Metal-Oxide-Semiconductor) devices. $Ta_2O_{5}$ thin film (63 nm) was deposited by ALD(Atomic Layer Deposition) method at temperature of 235 $^{\circ}C$. The structures of the $Ta_2O_{5}$ thin films were examined by XRD(X-Ray Diffraction). From XRD, it is found that the structure of $Ta_2O_{5}$ is single phase and orthorhombic. From capacitance-voltage (C-V) anaysis, the dielectric constant was 19.4. The temperature dependence of current density-electric field (J-E) characteristics of $Ta_2O_{5}$ thin film was studied at temperature range of 300 - 423 K. In ohmic region (<0.5 MV/cm), the resistivity was 2.456${\times}10^{14}$ ($\omega{\cdot}cm$ at 348 K. The Schottky emission is dominant at lower temperature range from 300 to 323 K and Poole-Frenkel emission is dominant at higher temperature range from 348 to 423 K.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.05c
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• pp.41-46
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• 2002

In this work, we studied electrical characteristics and leakage current mechanism of Au/$Ta_2O_5$/Si metal-oxide-semiconductor (MOS) devices. $Ta_2O_5$ thin film (63nm) was deposited by atomic layer deposition (ALD) method at temperature of $235^{\circ}C$. The structures of the $Ta_2O_5$ thin films were examined by X-Ray Diffraction (XRD). From XRD, the structure of $Ta_2O_5$ was single phase and orthorhombic. From capacitance-voltage (C-V) analysis, the dielectric constant was 19.4. The temperature dependence of current-voltage (I-V) characteristics of $Ta_2O_5$ thin film was studied from 300 to 423 K. In ohmic region (<0.5 MVcm${-1}$), the resistivity was $2.4056{\times}10^{14}({\Omega}cm)$ at 348 K. The Schottky emission is dominant in lower temperature range from 300 to 323 K and Poole-Frenkel emission dominant in higher temperature range from 348 to 423 K.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1995.11a
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• pp.209-212
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• 1995

In this paper, the $(Sr_{0.85}{\cdot}Ca_{0.15})TiO_3$ of paraelectric grain boundary layer (GBL) ceramics were fabricated. The characteristics of electrical conduction and the thermally stimulated current(TSC) were measured respectively. The region I below 200[V/cm] shows the ohmic conduction, the region II between 200[V/cm] and 1000[V/cm] can be explained by the Pool-Frenkel emission theory, and the region III above 2000[V/cm] is dominated by the tunneling effect. As a result, The origins of these peaks are that the ${\alpha}$ peak observed at $-20[^{\circ}C]$ looks like to be ascribed to the ionization excitation from donor level in the grain, and the ${\alpha}^{\prime}$ peak observed at $-20[^{\circ}C]$ appears to show up by detrap of the trapped carrier of border between the oxidation layer and the grain, and the ${\beta}$ peak observed at $80[^{\circ}C]$ seems to be resulted from hopping conduction of existing carrier in the trap site of the border between the oxidation and second phase.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.3
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• pp.41-47
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• 1999

Ion implanted GaAs MESFET with low resistive layer was fabricated using Si diffusion into GaAs from SiN. During the thermal annealing at 95$0^{\circ}C$ for 30s, Si diffused into ion implanted region of GaAs from SiN and they formed low resistive layer of 350$\AA$ thickness. The diffusion of Si decreased the sheet resistance of source and drain region from 1000$\Omega$/sq. to 400$\Omega$/sq. and the AuGe/Ni/Au ohmic contact resitivity from 2.5$\times$10sub -6$\Omega$-cmsup 2 to $1.5\times$10sup -6$\Omega$-cmsup 2. The fabricated lum gate length MESFET with Si diffused surface layer shows the transconductance of 360ms/mm, 8.5dB of associated gain and 3.57dB of minimum noise figure at 12GHz. These performances are better than that of MESFET without Si diffused layer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.04b
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• pp.69-72
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• 2002

We establish a visible light emission from porous polycrystalline silicon nano structure(PPNS). The PPNS layer are formed on heavily doped n-type Si substrate. 2um thickness of undoped polycrystalline silicon deposited using LPCVD (Low Pressure Chemical Vapor Deposition) anodized in a HF: ethanol(=1:1) as functions of anodizing conditions. And then a PPNS layer thermally oxidized for 1 hr at $900^{\circ}C$. Subsequently, thin metal Au as a top electrode deposited onto the PPNS surface by E-beam evaporator and, in order to establish ohmic contact, an thermally evaporated Al was deposited on the back side of a Si-substrate. When the top electrode biased at +6V, the electron emission observed in a PPNS which caused by field-induces electron emission through the top metal. Among the PPNSs as functions of anodization conditions, the PPNS anodized at a current density of $10mA/cm^{2}$ for 20 sec has a lower turn-on voltage and a higher emission current. Furthermore, the behavior of electron emission is uniformly maintained.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.743-746
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• 2003

We have successfully used hydrophobic direct-wafer bonding, along with H-induced layer splitting of Ge, to transfer 700nm think, single-crystal Ge films to Si substrates. Optical and electrical properties have been also observed on these samples. Triple-junction solar cell structures gown on these Ge/Si heterostructure templates show comparable photoluminescence intensity and minority carrier lifetime to a control structure grown on bulk Ge. When heavily doped p$^{+}$Ge/p$^{+}$Si wafer bonded heterostructures were bonded, ohmic interfacial properties with less than 0.3Ω$\textrm{cm}^2$ specific resistance were observed indicating low loss thermal emission and tunneling processes over and through the potential barrier. Current-voltage (I-V) characteristics in p$^{+}$Ge/pSi structures show rectifying properties for room temperature bonded structures. After annealing at 40$0^{\circ}C$, the potential barrier was reduced and the barrier height no longer blocks current flow under bias. From these observations, interfacial atomic bonding structures of hydrophobically wafer bonded Ge/Si heterostructures are suggested.ested.