• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2006년도 하계종합학술대회
• /
• pp.533-534
• /
• 2006

This paper presents the architecture design of a high-speed, low-complexity 128-point radix-$2^4$ FFT processor for ultra-wideband (UWB) systems. The proposed high-speed, low-complexity FFT architecture can provide a higher throughput rate and low hardware complexity by using 2-parallel data-path scheme and single-path delay-feedback (SDF) structure. This paper presents the key ideas applied to the design of high-speed, low-complexity FFT processor, especially that for achieving high throughput rate and reducing hardware complexity. The proposed FFT processor has been designed and implemented with the 0.18-m CMOS technology in a supply voltage of 1.8 V. The throughput rate of proposed FFT processor is up to 1 Gsample/s while it requires much smaller hardware complexity.

• 한국통신학회논문지
• /
• 제33권11C호
• /
• pp.940-948
• /
• 2008

본 논문에서는 휴대용 고속 무선 LAN 시스템에 적합한 저전력/저면적 MIMO-OFDM 기저대역 프로세서의 효율적인 하드웨어 구조를 제시한다. 고속 무선 LAN 시스템은 최대 수백 Mbps의 데이터 속도를 처리해야 하기 때문에 높은 시스템 클럭과 다중경로 구조를 사용하게 되는데, 이는 소모 전력과 구현 면적을 상승시키는 결과를 초래한다. 따라서 본 논문에서는 저전력으로 동작하면서도 동시에 하드웨어 부담을 줄인 고속 무선 LAN 시스템용 기저대역 프로세서의 하드웨어 구조를 제시한다. 이를 위해서 비트 병렬 처리 구조로 설계된 송신단 PLCP(TX-PLCP) 프로세서와 연산 복잡도를 효과적으로 감소시킨 심볼 검출기를 제안한다. 제안된 TX-PLCP 프로세서 구조는 비트 병렬 처리를 통해 동작 주파수를 감소시킴으로써 전력소모를 낮추는 효과를 얻을 수 있고, PMD 프로세서에서 가장 큰 면적을 차지하는 심볼 검출기는 수식 변형을 통해서 나눗셈 연산 및 제곱근 연산을 제거함으로써 저면적 설계를 가능하게 한다. 제안된 하드웨어 구조를 적용한 기저대역 프로세서는 Verilog HDL을 통해 설계 및 검증되었으며, 0.18um CMOS 공정을 통해 합성되었다. 합성결과, 병렬처리 구조를 적용한 TX-PLCP 프로세서는 비트 직렬 처리 구조에 비해 약 81% 감소된 전력에서 동작함을 확인하였고, 제안된 심볼 검출기는 나눗셈 및 제곱근 연산을 포함하는 심볼 검출 기법에 비해 약 18% 정도 하드웨어 복잡도가 감소함을 확인하였다.

• 디지털산업정보학회논문지
• /
• 제4권1호
• /
• pp.9-16
• /
• 2008

This paper presents a frequency selection algorithm for minimization power consumption of processor in Mobile System. The proposed algorithm has processor designed low power processor using clock gating method. Clock gating method has improved the power dissipation by control main clock through the bus which is embedded clock block applying the method of clock gating. Proposed method has compared power consumption considered the dynamic power for processor, selected frequency has considered energy gain and energy consumption for designed processor. Or reduced power consumption with decreased processor speed using slack time. This technique has improved the life time of the mobile systems by clock gating method, considered energy and using slack time. As an results, the proposed algorithm reduce average power saving up to 4% comparing to not apply processor in mobile system.

• IEIE Transactions on Smart Processing and Computing
• /
• 제4권2호
• /
• pp.71-77
• /
• 2015

Upcoming ground-breaking applications for always-on tiny interconnected devices steadily demand two-fold features of processor cores: aggressively low power consumption and enhanced performance. We propose implementation of a novel superscalar low-power processor core with a low supply voltage. The core implements intra-core low-power microarchitecture with minimal performance degradation in instruction fetch, branch prediction, scheduling, and execution units. The inter-core lockstep not only detects malfunctions during low-voltage operation but also carries out software-based recovery. The chip incorporates a pair of cores, high-speed memory, and peripheral interfaces to be implemented with a 65nm node. The processor core consumes only 24mW at 350MHz and 0.68V, resulting in power efficiency of $80{\mu}W/MHz$. The operating frequency of the core reaches 850MHz at 1.2V.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
• /
• 제5B권4호
• /
• pp.350-357
• /
• 2005

This paper presents a mechanical sensorless vector-controlled system with parameter identification by the aid of image processor. Based on the flux observer and the model reference adaptive system method, the proposed sensorless system includes rotor speed estimation and stator resistance identification using flux errors. Since the mathematical model of this system is constructed in a synchronously rotating reference frame, a linear model is easily derived for analyzing the system stability, including motor operating state and parameter variations. Because it is difficult to identify rotor resistance simultaneously while estimating rotor speed, a low-accuracy image processor is used to measure the mechanical axis position for calculating the rotor speed at a steady-state operation. The rotor resistance is identified by the error between the estimated speed using the estimated flux and the calculated speed using the image processor. Finally, the validity of this proposed system has been proven through experimentation.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2000년도 추계학술대회 논문집 학회본부 A
• /
• pp.174-176
• /
• 2000

In this paper, a high speed distance relay, using a digital signal processor(DSP) is presented. The idea of the protective algorithm is based on the least square method using minimum data window to minimize the relay operating time. A new disign concept for a low-pass filter is proposed. This analog low pass filter has minimum transient response time. The main processor of the relay is TMS320C31. According to a series of real time tests, the proposed protective relay shows reliable and fast operating characteristics.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
• /
• pp.321-324
• /
• 2001

This paper describes a fast and low-power multiplier co-processor architecture for digital signal processing applications and real-time control systems and its use as a multiplier co-processor for a 32-bit RISC microprocessor utilizing its one of the 16 co-processor interfaces. Its architecture adopts various algorithms to reduce the dynamic power and the area as well. The designed multiplier performs 32$\times$32 bit multiplication, and was designed using verilog HDL and 0.35${\mu}{\textrm}{m}$, 3V, 4M CMOS standard cell library. Its target operating speed is 40MHz, area lower than 10000 gate counts, and 10mW/MHz of power.

• 정보보호학회논문지
• /
• 제31권3호
• /
• pp.309-322
• /
• 2021

본 연구에서는 저성능 IoT 디바이스에서의 고속 암호화 연산을 지원하기 위해 블록암호 알고리즘 ARIA의 RISC-V 프로세서상에서의 고속 연산을 위한 확장 명령어 셋을 추가한다. 하드웨어상에서의 효율적인 구조로 ARIA 알고리즘을 구현하여 32bit 프로세서에서 동작하기 때문에 효과적인 확장 명령어 셋을 구현한다. 기존의 소프트웨어 암호화 연산과 비교하여 유의미한 성능 향상을 보인다.

• 대한전자공학회논문지SD
• /
• 제46권2호
• /
• pp.15-23
• /
• 2009

본 논문은 높은 데이터 처리율을 요하는 MIMO-OFDM 시스템을 위하여 고속의 낮은 하드웨어 복잡도를 가진 128/64-point $radix-2^4$ FFT/IFFT 프로세서 설계에 대해 제안한다. 높은 Radix 다중경로 지연 피드백 (MDF) FFT구조는 고속의 데이터 처리율과 낮은 하드웨어 복잡도를 제공한다. 제안하는 프로세서는 128-point와 64 Point FFT/IFFT의 동작을 지원할 뿐만 아니라 4-병렬 데이터 경로를 사용함으로써 높은 데이터 처리율을 지원한다. 또한, 제안하는 프로세서는 기존의 128/64-point FFT/IFFT 프로세서에 비해 낮은 하드웨어 복잡도를 지닌다. 제안된 FFT/IFFT 프로세서는 IEEE 802.11n 표준의 요구사항을 만족시키며 140MHz 클락 속도에서 560MSample/s의 높은 데이터 처리율을 가진다.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1990년도 추계학술대회 논문집 학회본부
• /
• pp.332-335
• /
• 1990

There are several methods in controlling resonant converters to regulate the output with low switching losses. In this paper, Pulse-width modulation method or current controlled method is applied to regulate the output with low switching losses. In digital implementation of resonant converter systems, the speed of the applied processor is very critical since the switching frequency is very high. Thus the various possible candidates of microprocessors are evaluated for the implementation of resonant converter systems. Then too design methods and techniques are desioribed when single chip processor is used to simplify hardware requirements.