A Low-power Muniplier Co-processor Design

저전력 승산기 보조 프로세서 설계

  • 이창호 (연세대학교 전기전자 공학과) ;
  • 곽승호 (연세대학교 전기전자 공학과) ;
  • 이문기 (연세대학교 전기전자 공학과)
  • Published : 2001.06.01

Abstract

This paper describes a fast and low-power multiplier co-processor architecture for digital signal processing applications and real-time control systems and its use as a multiplier co-processor for a 32-bit RISC microprocessor utilizing its one of the 16 co-processor interfaces. Its architecture adopts various algorithms to reduce the dynamic power and the area as well. The designed multiplier performs 32$\times$32 bit multiplication, and was designed using verilog HDL and 0.35${\mu}{\textrm}{m}$, 3V, 4M CMOS standard cell library. Its target operating speed is 40MHz, area lower than 10000 gate counts, and 10mW/MHz of power.

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