Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2001.06b
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- Pages.321-324
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- 2001
A Low-power Muniplier Co-processor Design
저전력 승산기 보조 프로세서 설계
Abstract
This paper describes a fast and low-power multiplier co-processor architecture for digital signal processing applications and real-time control systems and its use as a multiplier co-processor for a 32-bit RISC microprocessor utilizing its one of the 16 co-processor interfaces. Its architecture adopts various algorithms to reduce the dynamic power and the area as well. The designed multiplier performs 32
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