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http://dx.doi.org/10.5573/IEIESPC.2015.4.2.071

80μW/MHz 0.68V Ultra Low-Power Variation-Tolerant Superscalar Dual-Core Application Processor  

Kwon, Youngsu (SoC Research Department, Electronics and Telecommunications Research Institute (ETRI))
Lee, Jae-Jin (SoC Research Department, Electronics and Telecommunications Research Institute (ETRI))
Shin, Kyoung-Seon (SoC Research Department, Electronics and Telecommunications Research Institute (ETRI))
Han, Jin-Ho (SoC Research Department, Electronics and Telecommunications Research Institute (ETRI))
Byun, Kyung-Jin (SoC Research Department, Electronics and Telecommunications Research Institute (ETRI))
Eum, Nak-Woong (SoC Research Department, Electronics and Telecommunications Research Institute (ETRI))
Publication Information
IEIE Transactions on Smart Processing and Computing / v.4, no.2, 2015 , pp. 71-77 More about this Journal
Abstract
Upcoming ground-breaking applications for always-on tiny interconnected devices steadily demand two-fold features of processor cores: aggressively low power consumption and enhanced performance. We propose implementation of a novel superscalar low-power processor core with a low supply voltage. The core implements intra-core low-power microarchitecture with minimal performance degradation in instruction fetch, branch prediction, scheduling, and execution units. The inter-core lockstep not only detects malfunctions during low-voltage operation but also carries out software-based recovery. The chip incorporates a pair of cores, high-speed memory, and peripheral interfaces to be implemented with a 65nm node. The processor core consumes only 24mW at 350MHz and 0.68V, resulting in power efficiency of $80{\mu}W/MHz$. The operating frequency of the core reaches 850MHz at 1.2V.
Keywords
Processor; Core; Low-power; Variation-tolerance; Superscalar; Application processor;
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1 Y. Shin, et al., "28nm high- metal-gate heterogeneous quad-core CPUs for high-performance and energyefficient mobile application processor," Proc. of Int'l Solid-State Circuits Conference, pp. 154-155, 2013.
2 H. Kaul, et al., "A 320mw $56\mu{W}$ 411 GOPS/Watt ultra low voltage motion estimation accelerator in 65nm CMOS," IEEE Journal of Solid-State Circuits, vol. 44, no. 1, pp. 107-114, Jan. 2009.   DOI   ScienceOn
3 S. Jain, et al., "A 280mV-to-1.2V wide-operatingrange IA-32 processor in 32nm CMOS," Proc. of Intl. Solid-State Circuits Conference, pp. 66-68, 2012.
4 S. Das, et al., "A self-tuning DVS processing using delay-error detection and correction," IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 792-804, Apr. 2006.   DOI   ScienceOn
5 A. Raychowdhury, et al., "Error detection and correction in microprocessor core and memory due to fast dynamic voltage droops.", IEEE J. on Emerging and Selected Topics in Circuits and Systems, vol. 1, no. 3, pp. 208-217, Sep. 2011   DOI   ScienceOn
6 J. A. Poobey, et al., "A benchmark characteriation of the EEMBC benchmark suite," IEEE Micro, vol. 29, no. 5, pp. 18-29, 2009   DOI
7 K. A. Bowman et al., "Adaptive and resilient circuits for dynamic variation tolerance," IEEE Design & Test, vol. 30, issue 6, pp. 8-13, 2013   DOI
8 U. R. Karpuzcu et al., "Coping with parametric variation at near-threshold voltages," vol. 33, issue 4, pp. 6-14, 2013   DOI