Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A High-Speed 2-Parallel Radix-$2^4$ FFT Processor for MB-OFDM UWB Systems

MB-OFDM UWB 통신 시스템을 위한 고속 2-Parallel Radix-$2^4$ FFT 프로세서의 설계

  • Lee, Jee-Sung (School of Information and Communication Engineering Inha University) ;
  • Lee, Han-Ho (School of Information and Communication Engineering Inha University)
  • 이지성 (인하대학교 공과대학 정보통신공학부) ;
  • 이한호 (인하대학교 공과대학 정보통신공학부)
  • Published : 2006.06.21
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Abstract

This paper presents the architecture design of a high-speed, low-complexity 128-point radix-$2^4$ FFT processor for ultra-wideband (UWB) systems. The proposed high-speed, low-complexity FFT architecture can provide a higher throughput rate and low hardware complexity by using 2-parallel data-path scheme and single-path delay-feedback (SDF) structure. This paper presents the key ideas applied to the design of high-speed, low-complexity FFT processor, especially that for achieving high throughput rate and reducing hardware complexity. The proposed FFT processor has been designed and implemented with the 0.18-m CMOS technology in a supply voltage of 1.8 V. The throughput rate of proposed FFT processor is up to 1 Gsample/s while it requires much smaller hardware complexity.

Keywords