• ETRI Journal
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• v.39 no.1
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• pp.124-134
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• 2017

Data races are one of the most difficult types of bugs in concurrent multithreaded systems. It requires significant time and cost to accurately detect bugs in complex large-scale programs. Although many race detection techniques have been proposed by various researchers, none of them are effective in all aspects. In this paper, we compare the performance of five recent dynamic race detection techniques: FastTrack, Acculock, Multilock-HB, SimpleLock+, and causally precedes (CP) detection. We experimentally demonstrate the strengths and weaknesses of these dynamic race detection techniques in terms of their detection capability, running time, and runtime overhead using 20 benchmark programs with different characteristics. The comparison results show that the detection capability of CP detection does not differ from that of FastTrack, and that SimpleLock+ generates the lowest overhead among the hybrid detection techniques (Acculock, SimpleLock+, and Multilock-HB) for all benchmark programs. SimpleLock+ is 1.2 times slower than FastTrack on average, but misses one true data race reported from Mutilock-HB on the large-scale benchmark programs.

• Journal of IKEEE
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• v.22 no.4
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• pp.1158-1162
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• 2018

A fast-lock multiplying delay-locked loop (MDLL)-based digital clock frequency multiplier with an anti-harmonic lock capability is presented. The proposed digital frequency multiplier utilizes a new most-significant bit (MSB)-interval search algorithm to achieve fast-locking time without harmonic lock problems. The proposed digital MDLL frequency multiplier is designed in a 65nm CMOS process, and the operating output frequency range is from 1 GHz to 3 GHz. The digital MDLL provides a programmable fractional-ratio frequency multiplication ratios of N/M, where N = 1, 4, 5, 8, 10 and M = 1, 2, 3, respectively. The proposed MDLL consumes 3.52 mW at 1GHz and achieves a peak-to-peak (p-p) output clock jitter of 14.07 ps.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.281-284
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• 2001

This paper describes an analog multi-phase delay-locked loop (DLL) to solve the harmonic lock problem using current-starved inverter and shunt-capacitor delay cell. The DLL can be used not only as an internal clock buffer of microprocessors and memory It's but also as a multi-phase clock generator for gigabit serial interfaces. The proposed circuit was simulated in a 0.25${\mu}{\textrm}{m}$ CMOS technology to solve harmonic lock problem and to realize fast lock-on time and low-jitter we verified time interval less than 40 ps as the simulation results.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.05a
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• pp.691-693
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• 2017

A novel structure of fast locking phase locked loop (PLL) with time difference detector and Lock status indicator (LSI) is proposed in this paper. Fast locking time is achieved using LSI. It has been simulated and proved by HSPICE in a CMOS $0.18{\mu}m$ 1.8V process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.5
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• pp.410-415
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• 2011

In this paper, we investigated the fault current limiting and the load voltage sag suppressing characteristics of the flux-lock type SFCL, designed with the additive polarity winding, according to the variations of turn number's ratio and the comparative analysis between the resistive type and the flux-lock type SFCLs were performed as well. From the analysis for the short-circuit tests, the flux-lock type SFCL designed with the larger turn number's ratio was shown to perform more effective fault current limiting and load voltage sag suppressing operations compared to the flux-lock type SFCL designed with the lower turn number's ratio through the fast quench occurrence of the high-$T_C$ superconducting (HTSC) element comprising the flux-lock type SFCL. In addition, the recovery time of the flux-lock type SFCL after the fault removed could be confirmed to be shorter in case of the flux-lock type SFCL designed with the lower turn number ratio.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.499-500
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• 2006

This paper presents a fast switching CMOS frequency synthesizer with a new coarse tuning method for PHS applications. To achieve the fast lock-time and the low phase noise performance, an efficient bandwidth control scheme is proposed. Charge pump up/down current mismatches are compensated with the current mismatch compensation block. Also, the proposed coarse tuning method selects the optimal tuning capacitances of the LC-VCO to optimize the phase noise and the lock-time. The measured lock-time is about $20{\mu}s$. This chip is fabricated with $0.25{\mu}m$ CMOS technology, and the die area is $0.7mm{\times}2.1mm$. The power consumption is 54mW at 2.7V supply voltage.

• Journal of the Korea Safety Management & Science
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• v.17 no.3
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• pp.377-381
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• 2015

For the first time, PLL frequency synthesizer using DDS was adapted for the data link communication system which should fast transmit and receive each other with the correct information and fast Hopping System. It is inevitable to lost the synchronization by slow lock time about PLL and no cut off the noise. This paper propose the design of PLL frequency synthesizer which can make 800MHz frequency range. The PLL frequency synthesizer has three high qualities those are frequency accuracy, fast lock time and outstanding phase noise.

• The KIPS Transactions:PartA
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• v.10A no.3
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• pp.247-254
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• 2003

This paper describes a Delay Locked Loop (DLL) with low supply voltage and wide lock range for Synchronous DRAM which employs Double Data Rate (DDR) technique for faster data transmission. To obtain high resolution and fast lock-on time, a new type of phase detector is designed. The new counter and lock indicator structure are suggested based on the Dual-clock dual-data Flip Flop (DCDD FF). The DCDD FF reduces the size of counter and lock indicator by about 70%. The delay line is composed of coarse and fine units. By the use of fast phase detector, the coarse delay line can detect minute phase difference of 0.2 nsec and below. Aided further by the new type of 3-step vernier fine delay line, this DLL circuit achieves unprecedented timing resolution of 25psec. This DLL spans wide locking range from 500MHz to 500MHz and generates high-speed clocks with fast lock-on time of less than 5 clocks. When designed using 0.25 um CMOS technology with 1.8V supply voltage, the circuit consumes 32mA at 500MHz locked condition. This circuit can be also used for other applications as well, such as synchronization of high frequency communication systems.

• Proceedings of the KIEE Conference
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• 1997.11a
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• pp.456-458
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• 1997

The phase-lock technique is applied to a three-phase semi-bridge type battery charger system. Using an inner fast dynamic loop, the phase-locked voltage control (PLVC) technique of three-phase semi-bridge converter is proposed to give a frequency synchronism and to reduce the subharmonics due to the unbalance of transformer or power line. To protect the power devices, the two stage soft-start, function with softly locking the phase and softly increasing the current is presented. As limiting the reference voltage of the inner voltage control loop, muti-lock phenomena are removed on the PLVC loop. A current limit function is also proposed to limit the current of battery and converter. The proposed controller is confirmed through experiment results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.10-16
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• 2006

This paper presents a fast switching CMOS frequency synthesizer with a new coarse tuning scheme for PHS applications. The proposed coarse tuning method selects the optimal tuning capacitances of the LC-VCO to optimize the phase noise and the lock-time. The measured lock-time is about $20{\mu}s$ and the phase noise is -121dBc/Hz at 600kHz offset. This chip is fabricated with $0.25{\mu}m$ CMOS technology, and the die area is $0.7mm{\times}2.1mm$. The power consumption is 54mW at 2.7V supply voltage.