Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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An Efficient Coarse Tuning Scheme for Fast Switching Frequency Synthesizer in PHS Applications

PHS 어플리케이션에서의 빠른 스위칭 주파수 합성기를 위한 효율적인 Coarse Tuning 방법

  • 박도진 (건국대학교 전자공학부) ;
  • 정성규 (건국대학교 전자공학부) ;
  • 김진경 (건국대학교 전자공학부) ;
  • 부영건 (건국대학교 전자공학부) ;
  • 정지훈 (건국대학교 전자공학부) ;
  • 이강윤 (건국대학교 전자공학부)
  • Published : 2006.09.01
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Abstract

This paper presents a fast switching CMOS frequency synthesizer with a new coarse tuning scheme for PHS applications. The proposed coarse tuning method selects the optimal tuning capacitances of the LC-VCO to optimize the phase noise and the lock-time. The measured lock-time is about $20{\mu}s$ and the phase noise is -121dBc/Hz at 600kHz offset. This chip is fabricated with $0.25{\mu}m$ CMOS technology, and the die area is $0.7mm{\times}2.1mm$. The power consumption is 54mW at 2.7V supply voltage.

본 논문에서는 PHS 어플리케이션에서 새로운 Coarse Toning 기법을 사용한 빠른 스위칭의 CMOS 주파수 합성기를 기술하였다. 제안한 Coarse Tuning 방법은 Phase Noise와 Lock-Time을 최적화하기 위해 LC-VCO의 적절한 Tuning Capacitances를 선택하는 것이다. 이를 바탕으로 측정된 Lock-Time은 약 $20{\mu}s$ 이고, Phase Noise는 600kHz의 offset에서 -121dBc/Hz이다. 칩은 $0.25{\mu}m$ CMOS 공정으로 제작하였고, 면적은 $0.7mm{\times}2.1mm$ 이다. 소비전력은 2.7V 공급 전압 하에서 54mW 이다.

Keywords

References

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