• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.1-6
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• 2004

For MOSFET devices with nanometer range gate length, accurate extraction of effective gate length is highly important because transistor characteristics become very sensitive to effective channel length. In this paper, we propose a new approach to extract the effective channel length of nanometer range MOSFET by Capacitance Voltage(C-V) method. The effective channel length is extracted using gate to source/drain capacitance( $C_{gsd}$). It is shown that 1/$\beta$ method, Terada method and other C-V method are inadequate to extract the accurate effective channel length. Therefore, the proposed method is highly effective for extraction of effective channel length of 100nm CMOSFETs.s.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.130-133
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• 2011

A comparative study of two capacitance methods to measure the effective channel length in deep-submicron MOSFETs has been made in detail. Since the reduction of the overlap capacitance in the accumulation region is smaller than the addition of the inner fringe capacitance at zero gate voltage, the capacitance method removing the parasitic capacitance in the accumulation region extracts a more accurate effective channel length than the method removing that at zero gate voltage.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.653-657
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• 2015

A new paired gate-source voltage RF capacitance-voltage (C-V) method of extracting the effective channel length and parasitic capacitance using the intersection between two closely spaced linear regression lines of the gate capacitance versus gate length measured from S-parameters is proposed to remove errors from conventional C-V methods. Physically verified results are obtained at the gate-source voltage range where the slope of the gate capacitance versus gate-source voltage is maximized in the inversion region. The accuracy of this method is demonstrated by finding extracted value corresponding to the metallurgical channel length.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.679-682
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• 2003

Improvement in MOS fabrication technology have led to high-density high-performance integrated circuits with MOSFET channel lengths in the sub-micron range. For devices of the size, transistor characteristics become highly sensitive to effective channel length. We propose a new approach to extract the effective channel length of MOSFET by Capacitance-Voltage (C-V) method. Gate-to-Source, Drain capacitance ( $C_{gsd}$) are measured and the effective channel length can be extracted. In addition, compared to l/$\beta$ method and Terada method, which has been point out that it fails to extract the accurate effective channel length of the devices, we prove that our approach still works well for the devices with down to sub-micron regime.e.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.136-141
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• 2016

A phase-locked loop(PLL) with effectively increased capacitance by current modulator has been proposed. In this paper, the effective capacitance of loop filter is increased by using current modulator and it results in 1/10 reduction of capacitance in loop filter. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process. The simulation results show that the proposed PLL has the same phase noise characteristic and locking time of conventional PLL.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.698-701
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• 2016

A phase-locked loop(PLL) with effectively increased capacitance by current modulator has been proposed. In this paper, the effective capacitance of loop filter is increased by using current modulator and it results in 1/10 reduction of capacitance in loop filter. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process. The simulation results show that the proposed PLL has the same phase noise characteristic and locking time of conventional PLL.

• Journal of Electrochemical Science and Technology
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• v.13 no.4
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• pp.479-485
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• 2022

The power of energy storage devices is characterized by capacitance and the internal resistance. The capacitance is measured on an assumption that the charges are stored at the electrode interface and the electric double layer behaves like an ideal capacitor. However, in most cases, the electric double layer is not ideal so a constant phase element (CPE) is used instead of a capacitor to describe the practical observations. Nevertheless, another problem with the use of the CPE is that CPE does not give capacitance directly. Fortunately, a few methods were suggested to evaluate the effective capacitance in the literature. However, those methods may not be suitable for supercapacitors which are modeled as an equivalent circuit of a CPE and resistor connected in series because the time constant of the equivalent circuit is not clearly studied. In this report, in order to study the time constant of the CPE and find its equivalent capacitor, AC and DC methods are utilized in a complementary manner. As a result, the time constants in the AC and DC domains are compared with digital simulation and a proper equation is presented to calculate the effective capacitance of a supercapacitor, which is extended to an electrochemical system where faradaic and ohmic processes are accompanied by imperfect charge accumulation process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.90-96
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• 2006

A novel ${\Sigma}{\Delta}$ fractional-N PLL architecture for fast locking and fractional spur suppressing is proposed based on the capacitance scaling scheme. It changes the effective capacitance of loop filter (LF) by increasing and decreasing current to the capacitor via different paths with multiple charge pumps. The effective capacitance of loop filter (LF) can be scaled up/down depending on operating status while keeping LF capacitors small enough to be integrated into a single PLL chip. Fractional spurs suppressing have been achieved by reducing the magnitude of charge pump current when the PLL is in-lock without degrading fast locking characteristic. It has been simulated by HSPICE in a CMOS $0.35{\mu}m$ process, and shows flat locking time is less than $8{\mu}s$ with the small size of LF capacitors, 200pF and 17pF, and $2.8k{\Omega}$ resistor.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.395-398
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• 1999

In ac PDP(plasma Display Panel), the discharge characteristics is very important to display clear images. In this paper, we have studied the measurement of voltage transfer curves which show the discharge characteristics in AC PDP. The change of the effective wall capacitance during a discharge is also studied. These depend on lateral spreading of charge distribution and the strength of the discharge. As a parameter of the frequency, we observed the effects of the frequency in voltage transfer curves and in effective wall capacitance changes. As frequency increases, minimum sustain voltage and firing voltage decrease. In upper region of gap voltage the chance of the effective wall capacitance is independent of frequency.

• Journal of Electrochemical Science and Technology
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• v.8 no.1
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• pp.1-6
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• 2017

The conductivity of the electrolyte used plays a critical role in the optimization of the performance of electrochemical double layer capacitors. However, when the difference in the conductivities of different electrolytes is not significant (only 10-20%), the conductivity has little effect on the capacitance. On the other, unlike the conductivity and viscosity of the electrolyte, the cation size directly influences the capacitance. Cyclic ions have a smaller effective radius than that of the corresponding acyclic ions because the acyclic alkyl groups have a greater number of conformational degrees of freedom, such as the rotational, bending, and stretching modes. Consequently, because of the smaller effective size of the cyclic ions, cells containing electrolytes with such ions exhibit higher capacitances than do those with their acyclic counterparts.