• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.4
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• pp.707-714
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• 2012

After a single-stage, second-order, multiple-feedback ${\Delta}-{\Sigma}$ modulator and a two-stage, second-order MASH ${\Delta}-{\Sigma}$ modulator were analyzed and simulated using Simulink and Matlab and their characteristics were compared, the following result was obtained: 1) The two ${\Delta}-{\Sigma}$ modulators do not have group delay distortion. 2) The characteristics of the noise shaping are nearly identical. As a result of the noise shaping, the power spectral densities have slope of 40 dB/dec. 3) There was no spurious tone. 4) The input range of the two modulators is from -1 to +1 in common. 5) Because the output of the two-stage MASH modulator is 2-bits (4-levels), design of frequency dividers and charge pumps of PLL are more demanding.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.313-321
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• 2014

A low-power low-cost polar transmitter for EDGE is designed in $0.18{\mu}m$ CMOS. A differential delta-sigma modulator (DSM) tunes a three-terminal voltage-controlled oscillator (VCO) to perform RF phase modulation, where the VCO tuning curve is digitally pre-compensated for high linearity and the carrier frequency is calibrated by a dual-mode low-power frequency-locked loop (FLL). A digital intermediate-frequency (IF) pulse-width5 modulator (PWM) drives a complementary power-switch followed by an LC filter to achieve envelope modulation with high efficiency. The proposed transmitter with 9mW power dissipation relaxes the time alignment between the phase and envelope modulations, and achieves an error vector magnitude (EVM) of 4% and phase noise of -123dBc/Hz at 400kHz offset frequency.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.319-329
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• 2016

High-level design aids are mandatory for design of a continuous-time delta-sigma modulator (CTDSM). This paper proposes a top-down methodology design to generate a noise transfer function (NTF) which is compensated for excess loop delay (ELD). This method is applicable to low pass loop-filter topologies. Non-ideal effects including ELD, integrator scaling issue, finite op-amp performance, clock jitter and DAC inaccuracies are explicitly represented in a behavioral simulation of a CTDSM. Mathematical modeling using MATLAB is supplemented with circuit-level simulation using Verilog-A blocks. Behavioral simulation and circuit-level simulation using Verilog-A blocks are used to validate our approach.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.3
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• pp.184-196
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• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for precision measurement of current flowing through a secondary cell battery in a battery management system (BMS). The proposed modulator implements two switched capacitor integrators and a single-bit comparator with peripheral circuits such as a non-overlapping clock generator and a bias circuit. The proposed structure is designed to be applied to low-side current sensing method with low common mode input voltage. Using the low-side current measurement method has the advantage of reducing the burden on the circuit design. In addition, the ±30mV input voltage is resolved by the ADC with 15-bit resolution, eliminating the need for an additional programmable gain amplifier (PGA). The proposed a single-bit 2nd-order delta-sigma modulator has been implemented in a 350-nm CMOS process. It achieves 95.46-dB signal-to-noise-and-distortion ratio (SNDR), 96.01-dB spurious-free dynamic range (SFDR), and 15.56-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 400 for 5-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 670×490 ㎛2 and 414 ㎼, respectively.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.967-970
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• 2003

A new adder-and-accumulator (A$^2$C) adapted to pipelined Δ$\Sigma$ modulators is proposed in this paper. With the viewpoint of area consumption, registers are removed in the existing pipelined Δ$\Sigma$ modulator, and then adder and accumulator are merged. In order to optimize area consumption, speed and power consumption, dynamic carry look-ahead adder (CLA) is adopted in $A^2$C. Moreover, a guideline for the transistor sizing in CLA with regard to the minimization of the energy-delay-area product (EDAP) is proposed[1]. The proposed $A^2$C has been verified by HSPICE simulations.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.1
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• pp.104-110
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• 2006

The advantage of the DSM which employ multi-bit quantizer is the increased SNR at the modulator's output. Typically 6 dB improvement is effected for every one additional bit. But multi-bit quantizer evidently requires multi-bit DAC in the feedback loop. The integral linearity error of the feedback DAC has direct impact upon the system performance and degraded SNR of the system. In order to mitigate the negative impact the DAC has on the system performance, many DEM(Dynamic Element Matching) schemes has been proposed. Among the proposed schemes, four schemes(DER,CLA,ILA,DWA) are explained and its performance has been compared. DWA(Data Weighted Averaging) method shows the best performance of the all.

• Journal of IKEEE
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• v.17 no.4
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• pp.511-516
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• 2013

This paper presents a SDM using the FDPA technique. The FDPA technique is the added feedback path which is the delayed path of DAC output. The designed SDM increases the SNR by adding the delayed digital feedback path. The proposed SDM is easily implemented by eliminating the analog feedback path. Through the MATLAB modeling, the optimized coefficients are obtained to design the SDM. The designed SDM has a power consumption of $220{\mu}W$ and SNR(signal to noise ratio) of 81dB at the signal-bandwidth of 20KHz and sampling frequency of 2.56MHz. The SDM is designed using the $0.18{\mu}m$ standard CMOS process.

• ETRI Journal
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• v.36 no.6
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• pp.924-930
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• 2014

This paper presents a $0.13{\mu}m$ CMOS 3-level envelope delta-sigma modulation (EDSM) RF signal generator, which synthesizes a 2.6 GHz-centered fully symmetrical 3-level EDSM signal for high-efficiency power amplifier architectures. It consists of an I-Q phase modulator, a Class B wideband buffer, an up-conversion mixer, a D2S, and a Class AB wideband drive amplifier. To preserve fast phase transition in the 3-state envelope level, the wideband buffer has an RLC load and the driver amplifier uses a second-order BPF as its load to provide enough bandwidth. To achieve an accurate 3-state envelope level in the up-mixer output, the LO bias level is optimized. The I-Q phase modulator adopts a modified quadrature passive mixer topology and mitigates the I-Q crosstalk problem using a 50% duty cycle in LO clocks. The fabricated chip provides an average output power of -1.5 dBm and an error vector magnitude (EVM) of 3.89% for 3GPP LTE 64 QAM input signals with a channel bandwidth of 10/20 MHz, as well as consuming 60 mW for both channels from a 1.2 V/2.5 V supply voltage.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.906-909
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• 2006

This paper proposes a new body-effect compensated switch configuration for low voltage and low distortion switched-capacitor (SC) applications. The proposed circuit allows rail-to-rail switching operation for low voltage SC circuits and has better total harmonic distortion than the conventional bootstrapped circuit by 19 dB. A 2-1 cascaded sigma-delta modulator is provided for performing the high-resolution analog-to-digital conversion on audio codec in a communication transceiver. An experimental prototype for a single-stage folded-cascode operational amplifier (opamp) and a 2-1 cascaded sigma-delta modulator has been implemented in a 0.25 micron double-poly, triple-metal standard CMOS process with 2.7 V of supply voltage.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.43-51
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• 2013

This paper presents a design and implementation of a low power switched-capacitor 3rd-order delta-sigma modulator for a digital hearing-aid application. The power consumption is reduced by minimizing the output swing of integrators through optimizing the coefficients of modulator architecture and using class-AB output operational amplifiers. The modulator was implemented in a 130nm CMOS technology, and measured to have 79dB of SNR(Signal-to-Noise Ratio) in the signal bandwidth between 100Hz and 10kHz with an oversampling ratio of 160. The power consumption was $60{\mu}W$ from 1.2V power supply and the modulator core occupied $0.53mm{\times}0.53mm$.