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http://dx.doi.org/10.4218/etrij.14.0114.0176

3-Level Envelope Delta-Sigma Modulation RF Signal Generator for High-Efficiency Transmitters  

Seo, Yongho (Department of Electronic Engineering, Dong-A University)
Cho, Youngkyun (Communications & Internet Research Laboratory, ETRI)
Choi, Seong Gon (College of Electrical & Computer Engineering, Chungbuk National University)
Kim, Changwan (Department of Electronic Engineering, Dong-A University)
Publication Information
ETRI Journal / v.36, no.6, 2014 , pp. 924-930 More about this Journal
Abstract
This paper presents a $0.13{\mu}m$ CMOS 3-level envelope delta-sigma modulation (EDSM) RF signal generator, which synthesizes a 2.6 GHz-centered fully symmetrical 3-level EDSM signal for high-efficiency power amplifier architectures. It consists of an I-Q phase modulator, a Class B wideband buffer, an up-conversion mixer, a D2S, and a Class AB wideband drive amplifier. To preserve fast phase transition in the 3-state envelope level, the wideband buffer has an RLC load and the driver amplifier uses a second-order BPF as its load to provide enough bandwidth. To achieve an accurate 3-state envelope level in the up-mixer output, the LO bias level is optimized. The I-Q phase modulator adopts a modified quadrature passive mixer topology and mitigates the I-Q crosstalk problem using a 50% duty cycle in LO clocks. The fabricated chip provides an average output power of -1.5 dBm and an error vector magnitude (EVM) of 3.89% for 3GPP LTE 64 QAM input signals with a channel bandwidth of 10/20 MHz, as well as consuming 60 mW for both channels from a 1.2 V/2.5 V supply voltage.
Keywords
CMOS; envelope delta-sigma modulation, EDSM; power amplifier; polar modulator; RF transmitter; 3GPP LTE;
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