Journal of the Institute of Electronics and Information Engineers (전자공학회논문지)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Design of Low-Power 3rd-order Delta-Sigma Modulator

저전력 3차 델타-시그마 모듈레이터 설계

  • In, Byoung Wha (Dep. of Electronic and Computer Engineering, Hanyang University) ;
  • Im, Saemin (Dep. of Electronic and Computer Engineering, Hanyang University) ;
  • Park, Sang-Gyu (Dept. of Electronic Engineering, Hanyang University)
  • 인병화 (한양대학교 전자컴퓨터통신공학부) ;
  • 임새민 (한양대학교 전자컴퓨터통신공학부) ;
  • 박상규 (한양대학교 융합전자공학부)
  • Received : 2012.08.17
  • Published : 2013.04.25
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Abstract

This paper presents a design and implementation of a low power switched-capacitor 3rd-order delta-sigma modulator for a digital hearing-aid application. The power consumption is reduced by minimizing the output swing of integrators through optimizing the coefficients of modulator architecture and using class-AB output operational amplifiers. The modulator was implemented in a 130nm CMOS technology, and measured to have 79dB of SNR(Signal-to-Noise Ratio) in the signal bandwidth between 100Hz and 10kHz with an oversampling ratio of 160. The power consumption was $60{\mu}W$ from 1.2V power supply and the modulator core occupied $0.53mm{\times}0.53mm$.

디지털 보청기에 적합한 저전력 3차 델타-시그마 모듈레이터를 설계하였다. 적분기의 출력 스윙을 최소화 하도록 모듈레이터 구조의 계수를 최적화하고, AB급 출력단을 갖는 2단 연산증폭기와 switched-capacitor 구조를 사용하여 전력소모를 최소화 하였다. 본 모듈레이터는 130nm CMOS 공정을 이용하여 제작되었으며, 샘플링 주파수가 3.2MHz일 때 100Hz-10kHz의 신호대역에서 79dB의 SNR(Signal-to-Noise Ratio)이 측정되었다. 전력소모는 1.2V 전원전압에서 $60{\mu}W$에 불과하며 A/D 변환기 코어의 크기는 $0.53mm{\times}0.53mm$ 이다.

Keywords

References

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